Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: wbmw who wrote (238837)	8/15/2007 5:12:59 PM
From: Joe NYC	Respond to of 275872

wbmw, Oh I see. Then AMD's L3 is mostly a means of making up for the shortcomings of their non-shared L2. Why not just share the L2 cache, then? Too much of a penalty to local access time? I think shared L2 is just a one time, special situation in Conroe and Penryn. I doubt Nehalem will have shared L2. While it (shared L2) is an advantage for Intel currently, moving to quad core, Intel not only loses the shared property, it also has to go to FSB. For AMD in Barcelona shared L2 was a non-starter, hence L3. And yeah, sharing data between cores is one of the primary consideration, which is why exclusivity went away. So there will not be a great deal of overall memory latency reduction due to cache. Joe