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Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: wbmw who wrote (238905)	8/16/2007 12:39:07 PM
From: muzosi	Read Replies (1) \| Respond to of 275872

As for changes in the RTL, even if the cores stay absolutely pristine, you will still have your brand new top level RTL code (which rolls up the cache design changes with the rest of the design), and then either has to be re-synthesized, or laid out again using whatever custom design tools the back-end guys have at their disposal. i don't know what you do for a living but this sounds like the output of one of the ai machines which generate english sounding meaningless sentences from words which have a high probability of getting used together.

To: wbmw who wrote (238905)	8/16/2007 1:00:57 PM
From: combjelly	Read Replies (1) \| Respond to of 275872

"However, that doesn't mean the core doesn't need to be revalidated with a cache hierarchy change that may give it different timings, and may require tweaks to the fetch state machine." I will grant you the revalidation. But, that is about it. Fetching from the L3 across the crossbar should be no different that a fetch from memory or from the cache of another processor, either ondie or in another socket. "It may very well require that Z-RAM needs a brand new pipeline to prevent performance degradation, and that intuitively makes sense, when you realize that address generation is limited by the number of bits in the address, which gets larger as the cache grows bigger." Umm, again, the L3 is a decoupled module. Will its internals be different than a SRAM L3? Sure. Does that make a real difference to the core? No. Why should it? "As for changes in the RTL, even if the cores stay absolutely pristine, you will still have your brand new top level RTL code (which rolls up the cache design changes with the rest of the design), and then either has to be re-synthesized, or laid out again using whatever custom design tools the back-end guys have at their disposal." Stringing together buzz words again. Kudos on exercising your vocabulary. I will grant you that the L3 has to be synthesized and laid out. That is a big "duh". But having brand new top level code is meaningless drivel. AMD designed the L3 interface so that they could easily have different sizes of L3, if it existed at all, without doing the things you claim they have to do. "Now, if you consider it "smoke" and "FUD" to make the simple conclusion that AMD should use their designers effectively" Straw man. Sort of. It would take a lot of time and effort to identify all of the fallacies you have strung together here and it isn't really worth the effort. Suffice it to say, you've constructed an admirable edifice of intellectually dishonest arguments. All to defend your original attempt to show off your command of buzz words. You have a long track record of trying to bulldozer others and putting down anyone who objects. Really, it is quite pathetic.

To: wbmw who wrote (238905)	8/16/2007 1:24:23 PM
From: Joe NYC	Read Replies (1) \| Respond to of 275872

wbmw, You are making me repeat myself. I have already said that there needn't be any direct changes to the core. However, that doesn't mean the core doesn't need to be revalidated with a cache hierarchy change that may give it different timings, and may require tweaks to the fetch state machine. Core has to be re-validated? That is very far fetched. The processor has to be validated, but the core does not need to be re-validated. Joe

To: wbmw who wrote (238905)	8/16/2007 2:36:13 PM
From: Tenchusatsu	Respond to of 275872

Beamer, here's my view on the whole L3 ZRAM thing. Basically if AMD can manufacture it right alongside the processor, it's not that hard to add to the design, validate it, and synthesize it with minimal effort. Cache timings change all the time, big deal. A pipeline here or there might need to be reworked, so what? If AMD engineers can design, validate, and release Barcelona with just 3-6 months of schedule slippage, they can figure out how to make L3 ZRAM caches work. (Now all they have to do is put a muzzle on Hector and the other AMD execs and tell them to stop writing checks their employees can't cash.) My doubts with ZRAM, however, remain: - How come IBM isn't putting ZRAM caches on their processors? Aren't they using SOI? - I read somewhere that AMD is moving away from SOI in the far future. What then? - Everything I've read so far states that ZRAM is slower than SRAM. Wikipedia suggests that the smaller size of ZRAM can reduce trace delay, but I don't trust that Wiki is telling the whole story. Tenchusatsu