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To: TimF who wrote (239158)	8/21/2007 2:10:50 PM
From: wbmw	Respond to of 275872

Re: Why? LV3 is off of the cross bar, wouldn't it work like any other LV3, or main memory, or access from other processors, its just a request over the crossbar that comes back quicker than a main memory request (but slower than a SRAM LV3 request). Cache cells by themselves merely carry a bit of data. How you access that bit depends on dedicated logic that needs to know how long that bit takes to read and write data, where to find that bit in the cache array, how to decode the address into the way the cache is organized, how to space out subsequent accesses so that they don't conflict (an example is a read that is requested before the a previous write is finished), etc. Z-RAM does not operate like SRAM, and therefore, requires a different logic block to access it. The crossbar is not a magic router that is instantly compatible with anything that attached to it. At best, it has a standard interface that each attached block will copy. The cache block will contain a crossbar compatible interface, but as for the cache block itself, it will need to be designed from the ground up to be compatible with the manner in which Z-RAM reads and writes data.