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To: Petz who wrote (239497)	8/28/2007 8:06:18 PM
From: dougSF30	Read Replies (1) \| Respond to of 275872

I was surprised to see that >2 nodes (e.g., MP servers) will not be supported until 2H09. I wouldn't count on that. :) The Intel scheme can achieve 2-hop latency "most of the time" vs. 3 for AMD, but when it can't there's a big penalty. Try "almost always".

To: Petz who wrote (239497)	8/28/2007 8:39:49 PM
From: wbmw	Respond to of 275872

Re: I was surprised to see that >2 nodes (e.g., MP servers) will not be supported until 2H09. I hope this is not the case, but if it is, I can't say it's a surprise. Intel continues to execute poorly in the MP space, lagging the mainstream by about a year. Haven't they figured out yet that MP demands more than the DP space? I guess if AMD has a much better part, then it's their market to win.

To: Petz who wrote (239497)	8/29/2007 12:32:35 AM
From: fastpathguru	Read Replies (2) \| Respond to of 275872

The Intel scheme can achieve 2-hop latency "most of the time" vs. 3 for AMD, but when it can't there's a big penalty. I was surprised to see that >2 nodes (e.g., MP servers) will not be supported until 2H09. A) The latter kinda nullifies the former... B) According to none other than, yes, David Kanter @ RWT, (http://www.realworldtech.com/page.cfm?ArticleID=RWT051607033728&p=2) Barcelona's... Coherent Hypertransport also features a slight change that will improve latency for some transactions. When a K8 fetches a cache line into its L1D or L2, it has to snoop the system and wait for the results. In particular, the K8 will snoop memory and every other cache in the system; once it gets all of these responses, it can use the cache line it fetched. However, in Barcelona if a requested cache line is in the M or O state (meaning that memory has a dirty copy), the CPU does not wait to get the snoop response from memory, improving the transaction latency. COOL, Barcelona will have the same feature! fpg