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Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: Tenchusatsu who wrote (239541)	8/29/2007 3:08:50 PM
From: graphicsguru	Read Replies (1) \| Respond to of 275872

GG, > Understand that CSI is "speculative cache coherency." It's game changing. Huh? That's up to the requesting processor, NOT its bus cluster. Well, not really. First of all, the way HT works, the requesting processor basically can't get the possibly wrong info early enough to matter. CSI changes the messages in a way that makes this kind of speculation worthwhile. But it's more complex than you're thinking of. What happens when there are several reads and writes in flight? The processors have to cooperatively undo them. Just backing out and doing a new read is not enough. The memory may have changed again in the meantime, and you need to get an old value. The best way to reduce latency is not to go outside the processor in the first place. That's great when you can do it, but not good for apps with working sets much larger than any cache. And there are plenty of apps like that. Databases, for example.