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Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: fastpathguru who wrote (239559)	8/30/2007 2:00:50 AM
From: graphicsguru	Read Replies (1) \| Respond to of 275872

I don't design CPU's for a living, so I can't really fill in all the blanks for the worst-case complexity. But here's the type of crazy edge case that has to work correctly. Processors A and B both try to do atomic increments on cache line x at the same time that a top priority real-time DMA steals most or all of the bandwidth between A and B and the DMA tries to modify the same line. Cache line x is resident in processor C, which happens at that very moment to be trying to evict the line just as a dram refresh cycle begins on the corresponding memory address. Processor D had a write request started on the same cache line due to a branch that it just figured out was mispredicted. I don't know. That's for openers. Maybe I'm just not looking at this kind of situation correctly, and it's really simple as you say. Or maybe it's really complicated to get every last edge case to work with absolute backwards compatibility, and that's why it has taken Intel so long to put CSI together. At least, I'm glad my head isn't on the line when it comes to guaranteeing the schem is absolutely correct. Sounds like you're volunteering for the job.