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Technology Stocks : Advanced Micro vs Intel (AMD / INTC) -- Ignore unavailable to you. Want to Upgrade?

To: Elmer Phud who wrote (2438)	9/20/2007 11:25:08 PM
From: kpf	Read Replies (1) \| Respond to of 2596

elmer Considering that the DD is really derived from actual yield numbers DD is derived from defects. Now, _this_ is not difficult - as far as i see. Now, question for you, why wouldn't these failure mechanisms be visible at sort and included in the DD numbers? They are visible. They just don't fail always. They might work at a frequency out of spec. They might work at frequency within spec, but don't fit in a power envelope. They might work at frequencies and power within spec, but only for voltages out of spec. Etc.etc. BTW, you keep referring to parametrics but you don't define them. I'd need to define parameters dies must meet as soon as begin to fab chips. It's Intel for theirs and AMD for theirs to define so that these work with what they demand as platform-specs. They show up as a difference in device behavior compared to what you expect it to do Not quite. A transistor has several dimensions which determine its behaviour. You can only fab it with tolerances of several nanometers, in many dimension. Couple nanometers plus or minus in gate-length or other dimensions change the behaviour in how fast it can switch, how much current goes through in on-state, how much leakage you have etc.etc. This was always so - it's just that you can't shrink the tolerances of manufacturing as fast as you can shrink transistor dimensions, so variation has already become the dominant cause of yield-loss - and it only can become worse going forward, even if you can compensate a good portion of it in DFM. This is the point to start thinking from to understand nowadays manufacturing. The classical DD cases of shortcuts and broken wires are close to irrelevant for yields already. K.