Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: graphicsguru who wrote (243144)	10/31/2007 10:04:16 PM
From: Saturn V	Read Replies (1) \| Respond to of 275872

They are both leakage currents in the sense that they are parasitic unwanted currents, which did not exist for transistors fabricated on older technologies. Gate Leakage is unwanted current from the gate to the substrate, or source drain. This is ocurring because the gate oxides have become extremely thin, of the order of a few atoms. OFF state Leakage is the current flowing from the drain to source of an "OFF transistor", ie the transistor cannot be shut off. This can be remedied by using longer drain to source spacing, which dramatically degrades speed.Or else it can be remedied by using thinner oxides, which aggravates the Gate Leakage. It can also be remedied by using higher Vt for the transistor, which again clobbers performance. Typically circuit designers use High Vt devices for slow circuits, and Low Vt devices for fast circuits. Now now you see the circuit and process design trade off box. HiK dielectrics allow the use of thicker oxides and yet give you low OFF transistor leakage. The Quiescent Leakage problems will be gone for a few more process generations.But as we shrink the features, the same problem will be back again.