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To: combjelly who wrote (243145)10/31/2007 9:56:15 PM
From: graphicsguruRespond to of 275872
 
Chipguy knows more about this than I.

Thanks, comb. That makes sense.

Chipguy, or anyone else knowledgable, can you educate
us about the relative importance of the different
kinds of leakage?

For example, what are their relative magnitudes in
a traditional CMOS inverter on leading-edge processes?

And comb, isn't the gate leakage going to depend on
the gate voltage? In a traditional inverter, for example,
wouldn't the gate leakage be different depending on
whether the input is a zero or a one?


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