To: Pam who wrote (3081 ) 1/17/2008 11:28:26 PM From: Joe NYC Read Replies (2) | Respond to of 4590 Pam,I will add one more thing- Once the Spansion-Saifun merger is consummated in 1Q08, R&D expenses will go up disproportionately in the near term, without a matching rise in revs to leverage the higher OE's. So some of the cost savings from 300mm output will be pushed-out. Seifun had a small positive income. I am not sure how it would turn to large negative income once under Spansion umbrella. Part of the revenue that made Saifun profitable was revenue from Spansion, so any loss of revenue of Saifun offsets loss of expense for Spansion. The R&D expense of Seifun - Spansion already paid a portion of it - through license payment to Seifun. Now, instead, Spansion will make these payments in form of payroll checks. What will affect the road to profitability for Spansion (to a much greater expense) is the depreciation charges for SP1, which will start to hit the P&L statement. I think we will hear a lot in terms of EBIDTA.Eclipse will have tough competition from Samsung's OneNAND (SoC) and Sandisk's mDoC (MCP) solutions consisting of NAND and Logic+LPDRAM from Qimonda. Realistically, Spansion has no chance here beyond some low-end design wins. I am not that familiar with Eclipse's specs but OneNAND's performance specs are extremely good. OneNAND and mDoC both have their pros and cons and I have written about it on the Sandisk thread. I will try to find your posts. But one thing to keep in mind is that it has been about 5 years running now that NAND would take over huge portion of cell phone market, and people making those predictions are 0 for 5.Joe, do not waste your time doing this analysis. Spansion has absolutely no chance whatsoever even with Quad bit products because they are at least 2 nodes behind and lack financial resources and experience with immersion lithography. They are too far behind on the learning curve and they don't have much time with Cash burning. Toshiba/Sandisk are about to introduce 3 bits/cell NAND at 56nm which, from what I am hearing, will have good performance. Toshiba/Sandisk are also getting ready to move to 43nm very soon. Toshiba/Sandisk, Samsung are all familiar with and have experimented with CTF and they have poured Billions of dollars into floating gate and will move to CTF when the time is right. If you have paid attention to Spansion over last 2 to 3 years, Spansion process transitions have been actually faster than market. Well, you may say: it is easy when you are far behind, and it is true to some extend. But the fact is that Spansion is at 65nm now, 65nm 4-bit per cell is sampling, 45nm is running in R&D fab and it is supposed to enter production in 2H 2008. A big news for Q1 / Q2 would be if Spansion announces sampling of 45nm Mirrorbit, which would be a confidence boost that 45nm process technology is on track. Now, 45nm for Spansion is a bit of a wild card because, apparently, it is the first node to use immersion lithography, but if Spansion executes and is at 45nm before the end of 2008, I see nearly a process technology node parity. It may not turn out that way, but it is certainly a scenario that is not outside of realm of posibilities. Another thing to keep in mind is that Spansion has already mastered charge trapping, and has a whole bunch of patents in the area (now with Seifun, even more). The NAND players will not only have to master something that Spansion is already at volume production with, the NAND players will have to work around Spansion patents to do so - or enter a licensing agreement. I would not dismiss out of hand the possibility that Spansion will close the gap, or even get ahead in silicon die area / bit. But Spansion will still be processing 1/10 to 1/20 of the 300mm wafers, so an absolute cost per bit will be a challenge for Spansion - unless everyone else trips up during their transition to charge trapping.I am not that familiar with cost/bit for ORNAND but 16Gb MLC NAND chips could sell for under $5 before the year is over! I am not either, but I very much we are going to find out anytime soon. One reason is that largest dies Spansion produces aer still a fraction of die sizes of NAND players - generally 20 to 50 mm^2, where NAND players go to 100s of mm^2. Second reason is that Spansion has no incentive to even produce these size dies anytime soon, and has no incentive to fight loosing battle head to head with NAND players. Spansion competition is mainly Numonyx, and between the 2 of them, Spansion occuppies low to mainstream of the market, Numonyx occuppies mainstream to high end. So a much more pressing goal for Spansion is to displace Numonyx from the high end of the cell phone market occuppied by NOR players. so there is no point in producing 16Gb densities in 2008. Spansion is currently not in any market that has demand for densities this high.Forget about surpassing, Spansion is way, way behind on the cost curve and that gap is about to widen. There is absolutely no competition between Spansion sampling 65nm Quadbits with 10-20kwpm with someone who has already completed migration to 56nm 2 bits/cell with 170kwpm 300mm wafers at mature yields and ready to begin 43nm production and expanding wafer capacity to 360kwpm 300mm wafers by mid-2009! I see now that you are counting 56nm half node as a node, which clarifies a bit your earlier comment that NAND players are 2 nodes ahead - which seemed a bit far fetched. So, yes, I agree that Spansion is 1 node behind (which you count as 2) but the gap widening heavily depends on Spansion stumbling on 45nm. So yeah, one can have a higher confidence that Tosh will enter production at 43nm ahead of Spansion, and that chances of Toshiba stumbling are much lower. So while the confidence level, and probability to stumble (at 45nm) is higher for Spansion (production is still nearly a year away), you can't just count it as something that is given. And going from 45nm further is supposed to put floating gate players in the bind, so you can't just count on that not happening... Joe