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To: Joe NYC who wrote (3088)	1/18/2008 9:29:10 AM
From: bobs10	Respond to of 4590

You, q3CC: Now are we about the schedule where we are planning to be? Yes, I think as an industry, if you look at the business we are in, the 40, 45-nanometer migrations, these are late ’08 and I believe we are going to be consistent with the best-in-class memory company. me: As far as I can tell both Samsung and Toshiba only plan to be in the low 40s, dimension wise, at the end of 08. Given the much speculated about scaling disadvantages of floating gate starting at approximately the 40nm area one would have to consider MirrorBit at 45nm to be close to parity with NAND. When you take into account the simpler production process MirrorBit uses the nod might go to MirrorBit cost wise, but I've never been able to find any actual cost comparisons of ORNAND and NAND. Three bit per cell seems to be something the NAND people drag out when they start talking about scaling, but I can't find much to support it. SPSN on the other hand has had qbit out for quite a while at 90nm and now 65nm even though they haven't ramped the die size much. Not that qbit is that big a factor yet. It appears there are still significant problems with qbit to overcome. I'm relatively sure this also applies to Nand tribit.