To: Rink who wrote (3092 ) 1/18/2008 11:56:34 AM From: Pam Read Replies (1) | Respond to of 4590 Hope you don't mind me repeating it once, but your conclusion is incorrect if Spansion is more or less right here: Well, the only way we will find out is when they release the die size of their products! Due to the increased storage capacity per cell, MirrorBit Quad technology is capable of delivering up to 30 percent smaller effective cell size per bit than floating-gate MLC NAND Flash memory technology at the same process technology node. investor.spansion.com ; This press release makes a claim without releasing the die size. STM's 1Gb 65nm FG MLC (2b/c) NOR has a die size of 50.8mm2 (FACT) and if one does rough math, it would give 2Gb in 101.6mm2 and 4Gb in 101.6mm2 if they did 4b/c. If we now now give a 30% efficiency for MirrorBit technology, we get 4Gb MirrorBit Quad at 65nm in a die size of 71.12mm2 or 5.56Gb in 99mm2 which compares poorly with 8Gb 2b/c MLC NAND from Toshiba in a die size of 99mm2! So, either Spansion's press release is misleading or my math is wrong :-( Although, I must warn everyone that rough math is rough! Typically, the die shrinks a bit with higher capacity but still the difference is huge and I stand by my conclusions from rough calculations FWIW and I will not hesitate to say I was wrong if Spansion's claim is valid and you can do the same because you are saying my conclusions are incorrect!Even if their would be no (<=30%) advantage a 4Gb Mirrorbit Quad chip at 65nm would be approximately (in an ideal scaling situation) equate to a 8Gb MLC NAND chip at 45nm. (Or in other words a 4Gb Mirrorbit Quad chip would have the same size as a 4Gb MLC NAND chip at the same process node, provided there was no <=30% size advantage.) Theoretical graphs are fine for academic purposes. What ultimately matters is the actual, physical die size, all else being equal. Since Spansion hasn't released the die size information, we will have to wait until they or someone else releases that information.