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To: wbmw who wrote (247824)	2/14/2008 5:33:21 PM
From: gvatty	Respond to of 275872

cj and wbmw does this help answer your pipeline questions? Let me know because I'm too tired to read it. tbp.berkeley.edu

To: wbmw who wrote (247824)	2/14/2008 6:16:02 PM
From: combjelly	Read Replies (1) \| Respond to of 275872

"Better tell Intel to update their slides. They claimed 10 stages in their comparison foils with Pentium 4." Intel counts the stages funny. Here is a diagram. google.com See slide 6. "and a repipelining might have certainly contributed to enabling higher clock frequencies, even while keeping the number of critical stages the same." Almost certainly. "Many claimed that AMD designed the K7 core for their 0.18u process, even though they initially launched it at 0.25u." It is my understanding that a processor is usually designed for the process that follows the one it launches on.

To: wbmw who wrote (247824)	2/14/2008 10:07:13 PM
From: TGPTNDR	Respond to of 275872

wbmw, Re: Better tell Intel to update their slides. They claimed 10 stages in their comparison foils with Pentium 4.> That looks to me like a slide by Anand. In it he Sez the P6 has two Fetch stages. On the other hand, x86.org , which carries the Intel copyright from 1995, SEZ, on page 12, "The first three stages of the pipeline are the instruction fetch unit." Could be the documentation is wrong. Maybe they used a pentium when they were counting the stages? Or, maybe they changed the number of stages during the production run? (Maybe that's why the G-Hz model didn't run right?) Or, maybe the link I provided should have been called Deep Background Information for Developers? What's your SPIN? -tgp