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To: mas_ who wrote (248595)3/11/2008 10:47:11 AM
From: pgerassiRespond to of 275872
 
Mas:

This site shows both fused and small die SC Core 2 Solos:

sandpile.org

Of course Intel fuses a good deal of their non functioning DC dies. This is nothing new. The old Celeron had a L2 cacheless version that was a fused off P3. Also note that even though a L2 cacheless die size is listed, no L2 cacheless release dates or specifications are shown. Also note that all 512KB L2 cache versions must be fused off 1MB L2 cache dies since that isn't a die with that native. Also the dual cores with 3MB of L2 (2x in quads) are fused 4MB L2 dies.

Pete



To: mas_ who wrote (248595)3/11/2008 6:25:49 PM
From: wbmwRespond to of 275872
 
Circumstantial? How can you possibly deny it? The spec calls the measurements "die width" and "die length". These are not ambiguous terms. Unless you want to claim that Allendale somehow miraculously shrank to sub-90mm^2 in size, then it's obvious that Intel has a separate single core design.


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