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To: pgerassi who wrote (248608)	3/11/2008 12:03:41 PM
From: chipguy	Read Replies (1) \| Respond to of 275872

It is clear that Intel has engineered smaller die size variants of its standard dual core 4 MB 65 nm NGMA device. That is a costly exercise and the break even point of sales for doing so vs fusing off full size devices is fairly high perhaps in the tens of millions of units range. Intel may or may not recover defective full size devices as single core or reduced cache dual core SKUs but even if it does they represent an extremely small percent of total single core/reduced cache SKU sales.

To: pgerassi who wrote (248608)	3/11/2008 12:16:54 PM
From: Elmer Phud	Respond to of 275872

Mas stated that Intel fuses off dies to get SC and lower cache variants. And that is most definitely true. Correction Pete, mas said Intel fuses off defective DCs to make SCs. You have no evidence of that and Intel has a single core device to serve that purpose. If you want to argue that Intel fuses off defective half cache devices I will agree that Intel has the capability to do that but we don't know that they in fact do. If Intel's yields are as good as they claim then the supply would be very small. The rejects would fall into multiple categories of which non repairable cache (full cache that is) would be only a minor contributor. Those devices would require special handling and add complexity in manufacturing. Much easier to toss what few there are. Half cache could be just fully functional with half cache intentionally fused off for marketing reasons. Die cost would be low enough that they still make a good profit. I know of one Intel product line which all had half the cache disabled because it was intended for a low cost market and performed too well. It would encroach on highend sales if allowed to ship with full size cache.