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Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: chipguy who wrote (248688)	3/13/2008 12:33:49 AM
From: pgerassi	Respond to of 275872

Chipguy: You are so full of BS. You didn't read the document and by your comments, don't look at what the criticality of things are. The L1D cache has a high repairability, up to 6 repairs per section. L2 cache itself only has up to two repairs per section. The chances of a usable die are high even if a section is bad in the L2. Its nil on the L1 caches, TLBs or directories. There are two independent L2 cache units. If both are good, you have the full cache, if one is bad, you have half of the cache. On the low chance that both are bad, you have none and the die is thrown out. In the L2, a simple defect that connects two rows together is enough to blow an entire section. Ditto for two columns. As I stated, you may be good at looking at a single memory macro, but your comments show you lack the big picture oversight of the die as a whole. Also I never stated that row redundancies are rare, that's you putting words you wish I said as part of my statements. There are some choice words for people who do that. Pete