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To: Woerns who wrote (3742)4/4/2008 1:27:56 PM
From: BUGGI-WO  Respond to of 4590
 
@Intel - ICCSS
Also this was presented:

A 128Mb (256Mb MLC) 90nm phase-change memory is presented. A multi-level
programming algorithm is developed and embedded into the chip, demonstrating
2b/cell feasibility. Experimental results are presented for time zero and after 48h, 125°C
bake and 100k erase/write cycles.

BUGGI