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To: dougSF30 who wrote (252878)	6/5/2008 3:26:59 PM
From: Elmer Phud	Read Replies (2) \| Respond to of 275872

Doug Looking at anand's page on memory latency, he shows Nehalem at 4 cycles for L1 vrs 3 for Penryn. Intel's slide says L1 cache same as core uArch. So is the extra clock derived from his measurements or from some other Intel document? Where do these numbers come from?

To: dougSF30 who wrote (252878)	6/5/2008 3:34:50 PM
From: mas_	Read Replies (1) \| Respond to of 275872

You are confusing main-memory prefetching with inter-level cache fetching when you talk about disabling prefetching for certain FSB-constrained benchmarks on Penryn. 'inter-level cache fetching' is a complete figment of your imagination. Please point me to a technical description of this made up BS. prefetching does not "only work for non-random patterns". It does not "work" or "not work", but rather works better the more uniform the access pattern is. BS. It is a hindrance with random memory accesses because it fills your cache up with data that isn't used and only has to be evicted which is why it is disabled in many benchmarks. spec.org Disabled 'Hardware Prefetcher' in BIOS Disabled 'Adjacent Cache Line Prefetch' in BIOS spec.org Bios settings: Hardware Prefetcher: Disabled Adjacent Sector Prefetch: Disabled The 'numbers' are derived from an industry-standard benchmark, it showed what happened when the rubber hit the road.