To: pgerassi who wrote (252930 ) 6/6/2008 12:31:08 PM From: Elmer Phud Respond to of 275872 Dear Peteif design rules were all that great, Prescott would not have been poor originally. Prescott required a better process to meet its design targets than it had. There have been times that a process's design rules were bad. What was fine in the lab turned out to be bad in production. It took Intel 5 months to get something decent out. Well it took AMD over a year to get a broken Barcelona out but you are correct in pointing out the problems with Prescott and it was the inspiration for Intel's tick/tock design methodology. No more major changes combined with a new process. So you can't refer to that as a reason to expect poor Nehalem yields. The 45nm process is healthy. By your reasoning any silicon prior to production has zero yield, by definition. That's not a definition anybody else uses but it's also not the first time you've shown great creativity when redefining terms. Heck the fab can do a great job with 90% good working dies from a wafer, but the speeds of the resulting chips may be 1/2 of what is needed to sell. So the overall saleable yield is near zero. Or there could be a design flaw like FDIV where every die is bad. The problem wasn't in the fabrication, but the design. Again, redefining terms. Using your logic, because of the TLB bug all Barcelona silicon prior to B3 had zero yield. Perhaps we should also include all errata? If we do then all silicon shipping today, both from AMD and Intel, has zero yield. Using your reasoning, because with Barcelona AMD has never hit their frequency goals, AMD has had to lower their prices to dump their slow material, so they still have effectively zero yield. I would also point out that your experience of backend fallout having a major impact on overall yield is unfortunate. It's the result of not having your design and process tightly coupled. I hope your methodologies will improve in the future but without your own fab that's going to be essentially impossible. Binsplit was likely a factor for Intel as well during the P4 era but there is no reason to believe that it's a factor today. In fact anecdotal evidence suggests otherwise with easy overclockability and substantial availability from limited fab capacity. Clearly Nehalem is not production worthy today or it would be shipping, but the extensive functionality shown on A2 silicon is a good predictor, and combined with a healthy 45nm process, there is no reason whatsoever to expect development delays beyond what would be normal for any new product introduction. However I can certainly understand why you're hoping for it.