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To: pgerassi who wrote (252996)	6/7/2008 5:43:12 PM
From: misen	Read Replies (1) \| Respond to of 275872

I do know of one production semiconductor process that uses 200+ scans right off the top of my head, that of making VCSELs. They need a 30-60 pairs of alternating materials to do the mirrors at the top. Each layer takes two scans. Granted it is a special structure, but the results are well worth it for very high speed high data rate comm (>1TB/s). And yes they are SESP at a relatively wide process. They usually have the drive logic adjacent to the VCSEL. Long term they are looking at it to do interchip comm. First, if you are correct about 2 mask layers per material layer, 2x60 is not anywhere near > 200+. Even with any additional masking layers needed to create interconnects or drive circuitry, you are still far below 200. Second, I highly doubt that a VCSEL process patterns each material layer after it is deposited. It is far more likely that all the material layers are deposited together and then they are patterned as a stack (similar to the way that the oxide/poly 1/Oxynitride/Poly 2 stack was fabricated on some older EPROM processes). Do you have a link that substantiates your claim or are you just assuming that this is the case? I notice you didn't comment about either of my points relating to your error on masks required for metal/dielectric patterning as well as the small percentage of mask layers that would use double patterning. Misen