Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: misen who wrote (253014)	6/7/2008 10:54:21 PM
From: graphicsguru	Read Replies (1) \| Respond to of 275872

Misen, Forgive the ignorance (I know very little about lithography), but how do you etch multiple layers at once? I naively assumed that each layer had to be separately etched before the next layer was applied. And how do you put different patterns on different layers if they're etched in a single patterning?

To: misen who wrote (253014)	6/8/2008 12:27:49 AM
From: pgerassi	Respond to of 275872

Misen: No because there are more than one way to make VCSELs. And integrating them on logic chips like CPUs and GPUs isn't going to use one etch. But you knew that didn't you? No? Well then you need to rethink you ridiculous claim that 200+ scans is impossible. What do you think that MEMP is going to require for 22nm on 193i scanners assuming EUV is late? 4 quadruple length exposure scans per single photoresist layer. Thus your claim that 200+ scans will never be needed is ridiculous. Pete