Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: pgerassi who wrote (254156)	7/17/2008 1:43:09 PM
From: eracer	Read Replies (1) \| Respond to of 275872

Re: So the estimate for x1, x2, x3 and a part of x5 which comprise the core are likely to be even smaller than the estimate. Riiiiight. The reason I threw in the CPU scaling estimate at all was to show how tortured your logic was, and how silly it is for you to assume perfect scaling from 55-nm to 45-nm just so it can suit your calculations. Of course if the memory controller didn't scale in size at all Brisbane would still be two-thirds memory controller and 1/3 everything else. You also can't really use the x4 estimate for the ones on the CPU because GPU frame buffer memory is usually faster than main memory used in PCs. Thus it needs more current and thus more die area than a similar CPU version especially since the latter uses a more high performance process. AMD's 65nm SOI yields more current density than TSMC's 55nm bulk logic. The former is optimized for speed while the latter is optimized for yield. Yeah, that explains it. We are talking GPUs instead of CPUs. So do you also believe the RV670 die area is almost all memory controller? According to your calculations the 256-bit memory controller (64-bitx4) must take up almost 160mm^2 (~39.67mm^2 x 4) of the 192mm^2 die. Of course all this leads to a QAD estimate. Quick because it ignores certain things and dirty because of such things as dead areas, optimization, feature creep and different amounts of metal layers that throw them off... ...Thus your answers are whittled away due to glaring holes in your knowledge or purposely using poor assumptions to ridicule a method with some utility. They say, assumptions are the mother of all royal foulups (the nastier terms typically used are not allowed on this board). I see that you seem to do it a lot. And of course you still ignore real features like UVD which you are still pretending don't exist because they'd make the die size minus memory controller and PCIe far larger than you need it to be for your 20mm^2 Fusion core to be true.