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To: Elmer who wrote (37216)	10/21/1997 11:58:00 PM
From: Paul Engel	Respond to of 186894

Elmer - Re: "Does AMD's 5 metal layers plus local interconnects/buried contacts result in longer processing times compared to Intels .35u 4 metal layer process. Doesn't this need to be factored in when computing die costs? Isn't the real measure of die cost total good die per unit of time?" Excellent point - I didn't consider this. At the 0.35 micron process, AMD's is more complex than Intel's and that works against the smaller die size. First - shallow trench isolation - one extra mask step (maybe an implant as well. Second - Local interconnect - one extra mask to open source/drain regions, titanium/tungsten deposition step, and a masking step to define the titanium/tungsten interconnect. Third - For the 5'th layer of metal, a CMP step must be added after oxide deposition over the 4'th layer of metal, a via mask and etch must be performed, tungsten plugs must be deposited into the vias and anther CMP step is required to planarize the plugs/oxide, then a metal deposition is required as well as metal masking and etching. After passivation is deposited over the 5'th layer of metal, another set of vias must be opened for C4 bumps. But -AMD is not doing the C4 processing. The wafers have to be boxed up and packaged then shipped off to IBM somewhere. And it is IBM that performs the C4 solder bump deposition. All these steps probably add another week and half to two weeks. The C4 wafer processing/shipping has to be a logitical nightmare. Add in the cost of the extra equipment and this results in a very expensive wafer. If the yields are low (no IF about this!), the cost per yielded die skyrockets! Paul