Technology advances in chips to come at high price........................
infoworld.com
By Andy Santoni
InfoWorld Electric
Posted at 7:43 AM PT, Oct 23, 1997
SAN DIEGO -- Semiconductor process technologies such as finer features and larger wafers will enable faster, more feature-rich electronic products, but at a high cost and complexity, technologists were told at the Dataquest Semiconductor Conference here Wednesday.
Among the advanced technologies now coming on stream are design rules smaller than 0.3 microns; wafer size shifting from 200mm to 300mm; system-level integration; combining logic and memory on one chip; and copper replacing aluminum wiring, said Clark Fuhs, principal analyst at Dataquest.
With smaller features, however, semiconductor manufacturers have to be more concerned with mechanical defects on semiconductor wafers, Fuhs said. There is an "increasing need to minimize critical defect levels with narrowing design rules," he said.
Larger wafers, which will cut costs by allowing more chips to be produced in a single manufacturing lot, require more-expensive production equipment, Fuhs said. As a result, the transition from 200mm (8-inch) to 300mm (12-inch) wafers will not be quick, he said. Only about a dozen pilot facilities will be in place by the end of 2000, he projected.
Today's technologies are not sufficient for the task, said Mark Melliar-Smith, president and chief operating officer of Sematech, a consortium of 10 semiconductor companies based in Austin, Texas.
"Optical lithography is running out of steam," Melliar-Smith said.
To allow a shift to smaller devices in three or four years requires that semiconductor suppliers select one of the new technologies within the next year or two, Melliar-Smith said. That will give production equipment companies time to develop new hardware.
Semiconductor vendors will need to agree on a single next-generation lithography technology to keep costs down, Melliar-Smith said. The industry cannot afford to support three or four different technologies simultaneously, he said.
The new technology will also have to handle smaller feature sizes well into the future, Melliar-Smith said.
"I don't particularly want to go through this transition again in my lifetime," Melliar-Smith said.
Contenders to replace optical lithography are electron-beam, X-ray, or extreme ultraviolet, Melliar-Smith said.
Combining logic and memory, too, is not without its costs, said Inseok Hwang, senior vice president at Hyundai Semiconductor R & D division, in Korea. He said that Hyundai's DRAM process takes 18 mask steps, and the firm's logic process requires 21 steps. Combining the two raises the number of mask steps to 22 or 23, he said.
Peter Chang, president of Taiwan-based United Semiconductor, agreed. While one logic process might require 16 masking layers and a DRAM process might demand 20 of these process steps, the embedded DRAM process needed for system-level integration might need 25, he said.
"The cost is relatively high," Chang said.
The cost of a semiconductor production facility is also escalating, Chang said. His company's Fab-1, with an 8-inch capacity, will cost about $1.9 billion. The 12-inch Fab-2, slated to begin construction in 1999, will cost about $2.1 billion. By the time Fab-5 and Fab-6 are built, in 2003 to 2005, they will each cost $3.5 billion, he said.
"That cost will continue to rise," agreed Dale Harbison, vice president of Texas Instruments Semiconductor group, in Dallas. He, too, pegs the cost of a new fabrication today at about $1.5 billion.
These costs make it difficult to continue making improvements in semiconductor devices, Harbison said.
"The economics is what gets in the way," Harbison said.
Historically, transistor costs have followed a predictable curve, Harbison said. "We need to stay on that learning curve," he opined.
That imperative is clear in DRAMs, said Eiji Takeda, department manager in the System LSI Development office and Hitachi Ltd.'s Semiconductor and IC division. New manufacturing technologies will be needed with 16MB DRAMs for their prices to follow the pattern set by 256KB, 1MB, and 4MB parts, he said.
Among the technologies required to meet the demands of a system on a chip are embedded memory technology, 300mm wafers, and flexible, modular fabrication facilities, Takeda said. He noted that the capital investment for a 300mm production line to make 1GB DRAMs is 2.8 times that of a 200mm line to make 16MB devices.
Larger wafers will also require more automation in production, Melliar-Smith said. One reason is that the larger wafers are heavier, and a cassette full of 300-millimeter wafers is too heavy for a production worker to carry.
Harbison agreed. A full cassette of 300-millimeter wafers will weigh about 17 pounds, he noted.
Dataquest Inc., in San Jose, Calif., is at dataquest.com. |
