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Politics : RAMTRONIAN's Cache Inn -- Ignore unavailable to you. Want to Upgrade?

To: NightOwl who wrote (14416)	8/22/2009 5:03:03 PM
From: NightOwl	Respond to of 14464

The Toshiba/Sandisk vertical 3D-NAND was introduced at the 2007 VLSI: Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory Abstract We propose Bit-Cost Scalable (BiCS) technology which realizes a multi-stacked memory array with a few constant critical lithography steps regardless of number of stacked layer to keep a continuous reduction of bit cost. In this technology, whole stack of electrode plate is punched through and plugged by another electrode material. SONOS type flash technology is successfully applied to achieve BiCS flash memory. Its cell array concept, fabrication process and the characteristics of key features are presented. vlsisymposium.org They must be planning on stacking a heck of a lot of bit-layers and using algorithms to reduce the endurance problems of SONOS IP and the number of masks needed to produce it must be more than twice that required for either F-RAM, FeDRAM or FeNAND which all much simpler 2D designs. It will be a comparative power hog too I imagine. Anyway they are probably at least 2 years away from production if they indeed decide to produce it. 0\|0