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To: Ali Chen who wrote (1844)10/30/1997 1:11:00 PM
From: Brian Hutcheson  Read Replies (3) | Respond to of 6843
 
Ali , re. new implimentation of P6
That report states " a back side bus for L2 cache with 3.6 Gbits
back side bus" . Which translated means 450 mbytes or roughly the projected speed of the new CPU . Also when you factor in the 4 bytes in parallel , what they are really saying is , the CPU will run at 450Mhz and the external bus at 125mhz . Intel really hypes their products , Brian