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Technology Stocks : Altera -- Ignore unavailable to you. Want to Upgrade?

To: Bill Martin who wrote (1364)	11/1/1997 8:52:00 PM
From: Bilow	Read Replies (1) \| Respond to of 2389

It was my understanding that the Altera FPGA conversion, as well as the Xilinx conversion, consisted of replacing the RAM cells with ties to VSS or VCC. Thus you did save space, but logic was still implemented as multiplexors. I should explain: These FPGAs use multiplexors to provide logic functions. A 16 to 1 multiplexor is wired up with 16 ram cells at the input. These ram cells define an arbitrary function of four variables. The four multiplexor address lines are where you provide the function input. When they convert to FPGA, the ram cells are tied high or low, but the logic is still implemented by feeding the four inputs to address inputs. Consequently, a 4-input NAND gate uses as much space as a 4-input XOR gate, rather than much less as a full ASIC would use. This design technique means that they can implement it as a sea of gates sort of thing. That way they can share process steps between different designs. I.e, only the metalization layers differ. It also has the advantage that when your original design was done by a hone-head engineer who didn't design a synchronous system, you don't end up messing with the relative time delays as much as a conversion to a full custom. This reduces the probability of bringing an incipient race condition to life. If someone knows better, please correct me, I haven't turned an FPGA into the "hard-wired" version in about 3 years. -- Carl

To: Bill Martin who wrote (1364)	11/3/1997 10:46:00 PM
From: Ken Muller	Read Replies (1) \| Respond to of 2389

Bill: << Were they just selling a mask programmed version of your design on the same base silicon, or was it a "redesign" down to a smaller chip that only had the circuits your design requires?>> Just a masked programmed version <<Also do you know what the NRE charges are do do this conversion? Put another way, do you know how many chips you need to buy to break even between the cost of the ALTR FPGA and a cheaper ASIC conversion?>> Usually 10K devices/yr is the cutoff. NRE charges included in the price of the asic. Assumes no horrendous costs of re-qual.] Regards, Ken