SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Technology Stocks : The New QLogic (ANCR) -- Ignore unavailable to you. Want to Upgrade?


To: George Dawson who wrote (12166)11/2/1997 6:30:00 PM
From: Greg Hull  Respond to of 29386
 
George,

I know extremely little about data network design, however I know that in closed loop control higher bandwidth does not translate into tighter control automatically. Dead time (latency) reduction usually predominates over greater bandwidth when one wants to improve the quality of control. I suspect that some of the same issues apply to data transfer.

It is counter-intuitive that higher data speeds would not automatically result in lower latency, but I know this is not the case. I've never designed an ASIC, but I'm sure that some of the ways to skin the cat would compromise latency. A 1 gig Mk. II might outperform a 2 gig Silkworm in certain types of applications.

I wonder if ANCR marketing has identified the applications where Latency is King. It would be a shame to let that hard work of the ANCR ASIC designers go to waste.

Greg

P.S. maybe ANCR should call their products NanoWorks rather than GigWorks <g>.