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To: etchmeister who wrote (3779)	6/11/2010 8:31:38 AM
From: FJB	Read Replies (1) \| Respond to of 3813

TSV chips: Not ready for prime time Mark LaPedus (06/10/2010 10:02 PM EDT) URL: eetimes.com SAN JOSE, Calif. -- At this week's International Interconnect Technology Conference (IITC), some experts came to the same conclusion about 3-D chips based on through-silicon-vias (TSVs): It's not ready for prime time. This is based on observations from VLSI Research Inc., which attended the event. A plethora of companies, including ASE, Elpida, IBM, Intel, Samsung, Toshiba, TSMC and others, are exploring the possibly of stacking current devices in a 3-D configuration. Experts define a true 3-D package as one that stacks various chips vertically and then connects them by deploying through-silicon vias (TSVs). The aim is to shorten the interconnections between the chips, reduce die sizes and boost device bandwidths. So far, chip makers are shipping limited 3-D devices based on TSVs, mainly CMOS image sensors, MEMS, and, to some degree, power amplifiers. There are several problems with TSV technology: Lack of EDA design tools; complexity of designs; integration of assembly and test; cost; and lack of standards. As previously reported, Intel Corp. is still searching for an application for TSVs. “It does not make sense for Intel to go to 3-D with CPU cache memory,” said Mark Bohr, a fellow at Intel, at the event, according to VLSI. “It is due to interface speed issues.” ''Only CMOS image sensors are using TSV in production'' today,'' according to a report from VLSI Research. Memories with TSVs have been ''altar for three years. (The) bride has not arrived.'' For the most part, wire bonding has not run out of gas, as still 90 percent of I/Os are still using this technology, according to the firm. On the other hand, TSV is still a ''new and immature technology,'' according to VLSI. A chip-packaging technology cycle takes ''15-to-20 years,'' according to VLSI. ''Surface mount took 11 years to get to high volume. (But) it wasn’t dominant for 20 years. Area array packages took 12 years, (but they) still don’t dominate.'' And 3-D chips based on TSVs? Chip makers have been talking about this technology for a decade. But there are ''no significant quantities of 3D-TSV technology after 10 years,'' according to the firm. ''High-volume TSV is still some years away.''

To: etchmeister who wrote (3779)	6/21/2010 1:15:22 PM
From: FJB	Respond to of 3813

Trio forms 3-D chip alliance Mark LaPedus (06/21/2010 10:15 AM EDT) URL: eetimes.com SAN JOSE, Calif. -- Elpida Memory Inc., Powertech Technology Inc. and United Microelectronics Corp. (UMC) have formed an alliance to speed up the development of three-dimensional (3-D) chips at the 28-nm node as well as other processes. The 3-D devices will be based on through-silicon-vias (TSVs). This collaboration will leverage the strengths of Elpida's DRAM technology, Powertech's assembly, and UMC's foundry logic technologies to develop 3-D devices. This includes devices that integrate logic and DRAM. It's unclear which company will actually make the 3-D devices. The companies also did not announce a timetable. A plethora of companies, including ASE, Elpida, IBM, Intel, Samsung, Toshiba, TSMC and others, are exploring the possibly of stacking current devices in a 3-D configuration. Experts define a true 3-D package as one that stacks various chips vertically and then connects them by deploying TSVs. The aim is to shorten the interconnections between the chips, reduce die sizes and boost device bandwidths. So far, chip makers are shipping limited 3-D devices based on TSVs, mainly CMOS image sensors, MEMS, and, to some degree, power amplifiers. Elpida claims to have devised a DRAM based on TSVs. There are several problems with TSV technology: Lack of EDA design tools; complexity of designs; integration of assembly and test; cost; and lack of standards. But close integration of DRAM and logic technologies using TSV technology are expected to deliver the performance for a new class of chips. The UMC/Powertech/Elpida collaboration will facilitate the development of a total solution that includes logic/DRAM interface design, TSV formation, wafer thinning, testing and chip stacking assembly for customers. "Last year Elpida was the first to successfully develop an 8-gigabit DRAM based on TSV technology," said Takao Adachi, director and chief technology officer of Japan's Elpida Memory, in a statement. "The big advantage of this technology is that it enables a large number of I/O connections between logic and DRAM devices. This can massively increase the data transfer rate and reduce power consumption, making possible completely new kinds of high-performance devices,'' he said. ''However, we need a solid partnership with a logic foundry to make this happen. The joint development that we now plan with UMC means that we can use the most advanced TSV integration technology to bring together our advanced DRAM technology and UMC's leading-edge logic foundry technology including experience in providing SoC solutions such as advanced microprocessors,'' he said. ''Our plan now is to speed up development in a way that supports ultimate system solutions that will be made possible by freely joining together all kinds of devices through TSV integration."