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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Ali Chen who wrote (26089)	11/24/1997 11:44:00 PM
From: Yousef	Read Replies (2) \| Respond to of 1584064

Ali, Re: "How about this: ... lsilogic.com; Well Ali, I will comment on LSI's technology ... First, this process uses LOCOS isolation on a P substrate. This sort of isolation (versus shallow trench isolation) does NOT provide dense placement of NWell and PWell. These will be spaced further apart than with trench isolation. Notice, LSI didn't quote any SRAM cell size data. Second, the operating supply voltage is 2.5V for nominal operation. This means that the .18um quoted in this company HYPE is "probably" Leff data. Thus the printed gate length is closer to .28um. In fact, this process isn't even as advanced as Intel's .35um process !! Third, the interconnect pitches are very dense (typical of an ASIC process). this means that the Rs will be high and will not have optimal performance. If you disagree with this analysis, please post your thoughts. Make It So, Yousef