Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : C-Cube -- Ignore unavailable to you. Want to Upgrade?

To: Peter V who wrote (25584)	11/22/1997 9:11:00 AM
From: J Fieb	Read Replies (2) \| Respond to of 50808

TriMedia turns on digital TV By David Lammers What do you think BiilyG. Sounds too expensive for DVD players Yokohama, Japan - Philips Semiconductors described the latest version of its TriMedia processor at a one-day forum here. Philips said it expects the TriMedia 2 to be used in multifunctional, high-resolution digital TVs. The TriMedia 2 is a very long instruction word (VLIW) processor with performance of 5.4 billions of operations per second. That's enough to decode a high-definition (MPEG-2 MP@HL) signal on the processor itself, rather than going off-chip to a co-processor. MPEG high level (MPEG-2 MP@HL) requires about six times more processing power than MPEG-2 MP@ML, and Philips claims it will be the first chip supplier to combine MP@HL decoding on a main processor. The TriMedia 1000 first-generation device requires an external coprocessor to perform MPEG-2 high-level processing. When Philips began its TriMedia development project nine years ago, it devoted much of the effort to the compiler, which is normally the weak link in any VLIW design. "In RISC designs, when you get beyond a single-issue design the compiler becomes very tough. We have a five-issue slot, mapped to up to 27 functional units. Even the MMX processors are limited to two issues at best," said Selliah Rathnam, chief architect. The 2000-generation is software-compatible with the TriMedia 1000 series. Variable instruction length The TriMedia 2 is a five-issue VLIW design, able to handle five 32-bit operations in the same 6.66-ns cycle, said Rathnam. All five issue slots will be able to write to any of the chip's 27 function units. The instruction length is variable from 26 to 42 bits. Although VLIW processors are notorious for large code size, Rathnam said that the TriMedia 2 will compress instructions so that most variable-length instructions will require the minimum 26 bits. The chip includes 128 32-bit registers, and is capable of dual load-and-store operation. The TriMedia 2's main memory bandwidth of 1.1 Gbytes/second is much higher than the 400 Mbyte/s bandwidth of the TM1100, a version of the first-generation TriMedia design. The TriMedia 2 has a 64-bit memory interface and was designed to work with SDRAMs operating at up to 143 MHz. The output resolution must be able to support progressive displays, including plasma and projection large-screen displays, said Neil Mitchell, digital TV marketing manager for Philips. DTVs will need to be flexible and fast. With 18 possible video formats and counting, DTVs will be called upon to switch from one channel-perhaps broadcasting a high-definition signal sent to a 1,920-by-1,080 display-to a different channel of much lower resolution. DTVs will also support Web browsers and videoconferencing, and act as a mid-performance 3-D game platform. Philips was among a dozen non-Japanese companies which presented digital-TV solutions at the recent forum, sponsored by the Japan chapter of the Semiconductor Industry Association; the semiconductor users committee of the Electronics Industries Association of Japan; the European Electronic Components Association; the Korean Semiconductor Industry Association; and the International Semiconductor Cooperation group. TriMedia 2 will begin sampling in late 1998 and shipments will start the following year. That's about when DTV shipments will start in earnest, said Mitchell. techweb.com