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To: Rob S. who wrote (4897)	11/22/1997 3:15:00 PM
From: flickerful	Respond to of 11555

rob: bottom line....can they ramp quickly and efficiently enough?<eom>

To: Rob S. who wrote (4897)	11/22/1997 3:20:00 PM
From: flickerful	Read Replies (2) \| Respond to of 11555

<<The Hillsboro fab is supposed to be doing pilot runs of the 0.25 micron shrink. What is interesting is that they are going to add the integrated L2 cache - apparently before the C6+ version comes out.>> rob, for shipping how soon?

To: Rob S. who wrote (4897)	11/23/1997 4:40:00 PM
From: Gordon Quickstad	Read Replies (1) \| Respond to of 11555

<<The new 0.25-micron die would be so tiny that it would be pad-bound, so Centaur is adding an integrated L2 cache -- 256 KB, eight-way set-associative. It will retain the 32-KB L1 instruction cache and 32-KB L1 data cache already found on today's WinChips. >> This is an outstanding design innovation. The 8 way set-associative cache is a maximum efficiency cache as it allows up to eight different program threads that are executing at the same time and that have portions of their low order addressing which "map" onto each other, to all be able to get cache space. By contrast, the least efficient caching scheme is "direct map" or you can think of it as "one-way set associative" and it allows any programs that use the same low order addressing bits to be in contention for the same portion of the cache - each one booting the other out when they step on each other - a very inefficient scheme. The last water cooled IBM mainframes that i worked on used the 8-way cache - i don't know if there ever was a need to go beyond it because the comparison process to find out if a referenced address is in the cache becomes more complicated the finer the grain of the cache. Back then i used to figure that the use of a cache doubled the execution speed of a processor without a cache (that had to go to main memory all the time instead of being able to find instructions and data in a high speed cache).