Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Strategies & Market Trends : New US Economy Policy -- Ignore unavailable to you. Want to Upgrade?

To: Arthur Tang who wrote (84)	11/30/1997 5:59:00 AM
From: Arthur Tang	Read Replies (2) \| Respond to of 435

The new economy and Submicron technology in Semiconductor industry. The new economy is benefiting from the submicron technology because of the automation from computer speed and power. Semiconductor industry has been growing steadily. Now, comes the problem. When 0.5 micron rule change to 0.35 micron, yields of semiconductor production improved. Every semiconductor company made record earnings. The easy success, pushed investments into 0.25 micron rule. Gordon Moore of Intel with the simplistic Moore's rule never knew what disaster will hit the industry. AMD never knew why yields are no longer available to their production lines. The problem first lies in the software they used for designing the size of each transistor. Silicon wafers are limited in uniformity of resistivity. Most wafers today are supplied with 1 part per billion of dopants, to control the resistivity. When transistor size reduced to a tiny fraction of 1 billion atoms per transistor; the non-uniformity of distribution of dopants create transistor's failure to meet the specifications. Yields of large scale integrated devices with a few bad transistors becomes totally useless. Design software has to be calculating the aspic ratios to accomodate the uniformities in the silicon wafers. Zones on the silicon wafers where resistivity is uniform can have the same geometric sizes. Then, the isolation line width can not be scaled to the submicron rule, because the dielectric strength is at best 400 volts per mil. Any spike in switching will arc (six times the Vcc voltage)through the insufficient width. The production deviations within the guard band, can cause many CPUs to become dead on arrival. Cyrix had to retest to lower the Vcc ratings on some cpus made by IBM. Economy of semiconductor industry will suffer for a while, until design software for deep submicron line width technology can separate the line width advantage from the proper voltage design, and production yield vs. cost design, considerations. It may not take long, since programing software to reproportion the aspic ratio of transistor libraries is not a big job; if formulas can be learned from this disastries experience. The technology sector as a whole will recover early part of next year. AMD should be informed.