SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?


To: Ali Chen who wrote (26259)11/29/1997 11:40:00 PM
From: Elmer  Read Replies (3) | Respond to of 1572570
 
<The main reason why the Slot-1 CPU runs faster is the internal design methodoligy that Intel stole from DEC Alpha design - a RISK-like "short-tick" approach, when the complex logic is broken into longer processor pipelines. >

Ali, this isn't what Dec claimed Intel copied. What you have described is basic to all RISC designs, nothing unique to Dec.
In addition, AMD used these same techniques in designing the K6. You can make all the excuses you want but it won't change the fact that Intel has a better .35u process than AMD, and they have had it much longer. Some of the process steps may have come from Sematech, but certainly not all of them. Most of it was developed at Intels development fab, just like AMD developed their own too.

<If you would ask why the Slot-1 design shows slightly better performance, the answer is: due to additional "back-side" bus into L2 cache. AMD is going to fix this in K6+3D chip with on-chip L2 cache, as per my understanding. >

The backside bus does help, no question there and AMD will close some of the gap in doing their own version, but Intel's split transaction bus archeticture also contributes. This is why the Intel design is so effective is SMP servers and why you don't see any socket7 SMP servers.

EP



To: Ali Chen who wrote (26259)11/29/1997 11:45:00 PM
From: Yousef  Read Replies (1) | Respond to of 1572570
 
Ali,

Re: "In my opinion, the tiny differences in process implementation do not play significant role
in the final speed grade of a CPU. The basics of the process was developed at Sematech
and transferred equally to all members of the consortium."

Ali, please stick to technical areas that you which you know something ...
SEMATECH has not transferred an entire process to any of the member companies.
Instead, SEMATECH focuses on developing some unit processes and working
closely with vendors to give future specifications. Also, member companies
have always insisted that SEMATECH play no role in device architecture
design, development and verification. This is viewed by the member companies
as a "competitive advantage", so NO sharing in this area. I guess Ali,
you will have to learn the hard way (with your dollars) that there is
a big difference in process implementation. This will become even clearer
at .25um.

Make It So,
Yousef