OT
Gary, Something to look into!
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Wednesday December 3, 12:00 pm Eastern Time
Company Press Release
SOURCE: Teradyne
Teradyne ARIES System Delivers Single-Pass RAM Testing At 1 Gbit/Second, Provides Lowest Cost to Test in Production
TOKYO, Dec. 3 /PRNewswire/ -- A new Teradyne platform for testing high- bandwidth RAMS is being introduced at Semicon Japan this week. The ARIES RAM test platform, which operates at data rates to 1.0 Gbits/second while testing up to 16 devices in parallel, is designed for the newest-generation devices such as Direct Rambus(TM) DRAMs, SLDRAMS, and fast SSRAMs. By leveraging the proven, successful technologies of Teradyne's Marlin memory test platform and J973 logic test systems, the ARIES platform enables high-performance device testing at the lowest cost to test, said Glenn Farris, ARIES Product Manager. Teradyne also announced that it has received initial orders for ARIES systems, with deliveries beginning in the first quarter of 1998.
The High-Bandwidth Test Requirement
Direct Rambus-generation technology has changed the memory test requirement, Farris said, because it combines a high bandwidth logic interface bus with a high-density DRAM. ''When high-bandwidth RAMs are used in computers and advanced communications devices, a memory cell that fails at the new higher operating speeds can result in a spreadsheet error or a corrupt database,'' he said. ''Customers can't tolerate that.''
The solution is to test the performance of the whole memory in a single pass, at its full operating speed, including the array, the interface, and the complex interactions between them, Farris said. ''Without that kind of comprehensive testing, you're susceptible to gaps in fault coverage. Problems like bank interactions and noise sensitivities may not be found if the interactions between the array and the interface are not tested. Full functional algorithmic testing at speed enables the memory supplier to guarantee the total performance of high-bandwidth memories for computer and advanced communications applications.''
Teradyne's technology for testing these new devices has been proven. ''Teradyne demonstrated high-speed testing of the Rambus interface at the International Test Conference last month on the J973 VLSI Test System. We have proven that our technology meets the performance challenge of this interface,'' Farris said. ''However,'' he added, ''the interface might only comprise a small percentage of the silicon on the chip. ARIES' unique contribution is that it provides the full functionality to test the high-performance memory behind the interface, and find all the faults in the whole device.''
Lowest Cost to Test
Although test performance requirements have increased dramatically, memory production economics cannot change, Farris said. Manufacturers require the lowest cost per bit in order to win in the competitive memory marketplace. ARIES enables memory manufacturers to achieve the lowest cost to test in several ways:
Low Production Test Costs. By providing a test solution that includes single-pass high-speed testing, with the highest parallelism and throughput, ARIES enables manufacturers to realize the lowest possible cost to test. ARIES tests up to 16 devices in parallel at Gbit/second data rates; its Pin Slice(TM) architecture delivers fast DC testing and lowest test-time overhead. Fast Ramp-up to Volume Production. ARIES' production-proven software, full integration of handling equipment, and compatibility among test systems across the production floor speeds a manufacturer's ramp-up to volume production. Shortest time to Maximum Yield. ARIES provides algorithmic testing at speed, a powerful suite of silicon debug tools, and the RA/Plus(TM) redundancy analyzer, which finds every repairable die, to deliver the highest possible yields, in the shortest time. ARIES' 1 Gbit Catch RAM and Data Searcher compression hardware provide fast fail capture for redundancy repair analysis, silicon debug, and yield improvement engineering. Because ARIES' debug and characterization tools are fully integrated with its parallel operating software, memory manufacturers can perform fast data capture and analysis in parallel, reducing the time required to achieve maximum yields.
ARIES Leverages Proven Technology
The ARIES platform leverages technology proven in Teradyne's J973 and Marlin logic and memory test systems, which have been selected by the world's leading semiconductor producers, Farris said. ARIES' comprehensive memory test capability is based on Teradyne's 35+ years as a memory test leader; it includes at-speed algorithmic pattern generation, redundancy analysis, and parallel bit mapping. ARIES-platform systems also include the full logic test capability of the J973 VLSI Test System, whose innovative Pattern Integrator(TM) architecture was designed to provide seamless testing of devices combining complex logic and memory cells, with a pattern depth of up to 16M vectors for at-speed testing with no dead cycles. The system's advanced pin electronics includes low-jitter high-speed clocks and high-speed drivers for edge placement repeatability of +50 ps. In addition, ARIES' direct-connect test head design and fly-by handler contactor technology deliver high-speed test signals for at-speed performance testing.
Rambus Technology Partner
In September of this year, Rambus, Inc. announced that Teradyne was selected as a test technology partner for the Direct Rambus device. Several ARIES features have been designed in collaboration with Rambus to focus on the testing needs of high-speed DRAMs, Farris said. ''Rambus values the partnership we have with Teradyne to develop test solutions for the Direct RDRAM,'' said Allen Roberts, vice president and general manager of Rambus Inc [Nasdaq:RMBS - news].'s Memory Technology Division. ''Because Teradyne is a leading supplier of high-volume production memory test systems, its development of Direct RDRAM test solutions ensures that the test infrastructure is in place to rapidly bring our high-bandwidth interface technology to volume.''
Pricing of ARIES Platform systems starts at approximately $1.3 million. System shipments are approximately 18 weeks ARO.
Teradyne is a leading manufacturer of automated test equipment and connection systems for the electronics and telecommunications industries. The Memory Test Division is co-located in Agoura Hills and San Jose, California. Teradyne is listed on the New York Stock Exchange (Symbol: TER). Sales for the first three quarters of 1997 were approximately $875 million.
ARIES Specification Summary
Maximum Clock Rate 800 MHz
Maximum Data Rate 1.0 Gbit/sec
Edge Placement Timing + 50 ps repeatability
Minimum Pulse Width 1.0 ns
I/O Channels 512 separate I/O (fly-by configuration)
1,024 total I/O
Parametric Measurement Units 1 per I/O channel
Catch RAM 1 Gbit
Redundancy Analysis R/A PLUS(TM) software
Data Searcher compression hardware
Pattern Generators Full algorithmic memory pattern
generator
Logic pattern generator capacity for up
to 1 6 M vectors
Pattern Integrator architecture for
seamless switching between algorithmic
Direct Rambus is a trademark of Rambus, Inc. Pattern Integrator, RA/Plus and Pin Slice are trademarks of Teradyne, Inc.
SOURCE: Teradyne |
