To: DiViT who wrote (26071 ) 12/3/1997 8:47:00 PM From: Maverick Respond to of 50808
REAL-TIME MPEG-2 ENCODER AND MOTION ESTIMATION CHIP JOINS SONY'S VIRTUOSO(tm) FAMILY LAS VEGAS, COMDEX Booth #L2225, Nov. 17, 1997 -- Sony Semiconductor Company of America (SSA), a division of Sony Electronics Inc., today announced the CXD1922Q, a real-time MPEG-2 video encoder LSI. Benefiting from Sony's years of experience developing MPEG-2 technologies, the company's new integrated circuit features the industry's widest motion search area and integrates MPEG-2 encoding, systems controller and motion estimation circuitry into a single chip. The highly integrated CXD1922Q is a low-power, high-performance chip targeted toward low-cost solutions in consumer product, video server storage media, communications and digital versatile disk (DVD) authoring applications. "With the introduction of DVD, digital broadcasting and other new systems, the use of the MPEG-2 compression standard to store and transmit massive amounts of high-quality video has increased," said Vishwanath Nayak, director of marketing for consumer a/v/d division, SSA. "The CXD1922Q offers the most cost-effective MPEG-2 encoding solution ever offered in the semiconductor marketplace." "Because MPEG-2 video compression requires complex computational horsepower, previous products did not address lower-end markets. Until now, several LSI chips were required to implement MPEG-2 encoding, which was cost-prohibitive to most users," said Nayak. The CXD1922Q uses an advanced adaptive motion estimation algorithm developed by Sony for efficient video compression processing. The chip offers a search range of -288 to +287.5 horizontal pixels and -96 to +95.5 vertical pixels, at half-pixel accuracy, allowing high-quality encoding of rapidly moving scenes and video taken with fast camera movements. The CXD1922Q also supports dual prime encoding for applications which require short delay times. The Sony CXD1922Q supports MP@ML and SP@ML with image sizes up to 720x480 at 30fps for NTSC applications and up to 720x576 at 25fps for PAL applications. Full D1 resolution, single-pass encoding at 15Mpbs for I, P and B frames and 25Mbps for I frame is incorporated as well. The chip provides support for constant and variable bit rates, and automatic 3:2 pull-down inversion when required. With the use of 0.4 micron CMOS technology, original cell designs and an internal PLL with multiclock generation system, the CXD1922Q achieves high integration and low power consumption. The internal encoding controller allows functions such as timing, complex motion control and bit-rate control to be handled within the CXD1922Q for high-quality images and host independent operation. The CXD1922Q, packaged in a 208-pin QFP, supports a 16-bit controller host interface, accepts a 4:2:2 YUV CCIR656 (8-bit) parallel video input and outputs an MPEG-2 video elementary stream. The chip requires just 32Mbit of SDRAM and is rated at 1.2W for power consumption. Customer sampling of the Sony CXD1922Q is scheduled for January 1998, with an initial sampling price of $600. Manufacturing is expected to begin in second quarter of 1998.