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Technology Stocks : CYRIX / NSM -- Ignore unavailable to you. Want to Upgrade?

To: Investor A who wrote (21775)	12/5/1997 12:34:00 AM
From: Joe NYC	Read Replies (1) \| Respond to of 33344

Software Spiral, Intel Profits Both Stall mdronline.com Joe

To: Investor A who wrote (21775)	12/5/1997 1:04:00 AM
From: Joe NYC	Read Replies (3) \| Respond to of 33344

Here is something from MDRonline: (pretty old info) mdronline.com By eliminating the overhead of tag lookups and synchronization to an external 66-MHz bus, the MediaGX's DRAM controller can read the critical first word from memory in 6 CPU cycles on a page hit, exactly the number of cycles it takes a 133-MHz Pentium to access its L2 Cache. This speed essetially eliminates the need for external cache on MediaGX systems. Of course MediaGX takes longer to access DRAM on a page miss. The hit rate of Pentium's L2 cache is likely to be somewhat better than the hit rate of the DRAM page buffers, however, reducing the performance of the MediaGX relative to Pentium with L2 cache. If both processors are without L2 cache, the Cyrix will clearly do better. The MediaGX does not support the L2 cache, as there is no appropriate place to connect one. I think the performance contest between cacheless P-II 266 (32K L1) and cacheless MXi starting at PR-300 (64K L1) with it's superior memory architecture will be won by MXi hands down. If you add 128 bit memory access of MXi, MXi may be performing 50% better. If Cyrix delivers good things will happen to our investments ;-) Joe PS: How big is a DRAM page? PPS: is it possible that Cyrix is using the 128 bit memory bus in calculating the PR or is it going to be a bonus on top of the regular PR calculation?