Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : AMD:News, Press Releases and Information Only! -- Ignore unavailable to you. Want to Upgrade?

To: greg nus who wrote (2780)	12/7/1997 4:21:00 PM
From: StockMan	Respond to of 6843

Nusance, AMD's lack of R&D spending on the Flash area is the reason for this. With all of AMD concentrating on the K6, the other product lines have been neglected. AMD's road to bankruptcy is now downhill territory. Stockman

To: greg nus who wrote (2780)	12/7/1997 6:52:00 PM
From: Brian Hutcheson	Read Replies (2) \| Respond to of 6843

Greg , thanks for PH post That's typical of Paul's posts , he does not try to inform he tries to impress . The wisest of all men , put the most content in the least amount of words . On the other hand politicians and obviously some in the scientific world do the opposite , the least amount of content in the most verbiose way . One comment I would like to make on his post , he asks of what use is this non-volatile addition to the cpu ? The answer , to have a serial number which can't be removed so that in the event of theft the processor can be traced . My answer at the rate Intel is cutting their prices very soon they will be giving them away so why would anyone steal them , regards , Brian

To: greg nus who wrote (2780)	12/8/1997 3:38:00 PM
From: Petz	Respond to of 6843

greg, re:<polysilicide fuses and redundancy in memory> I've "burnt" many of the bipolar Intel PROM's in yesteryear, in fact, we also used to use the trick of "re-burning" them to patch the code (you could turn 0's into 1's but not 1's into 0's). Intel already uses the redundant memory in their Pentium II, I believe, since they use an error correcting code (ECC) in the L1 cache. I never understood why they bothered, but clearly the ECC can correct for silicon defects in a few cells of the SRAM because it is unlikely that two errors would occur in the same word and all single bit errors are correctable by the ECC. Petz