SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?


To: J_F_Shepard who wrote (890642)9/29/2015 10:41:40 PM
From: combjelly  Respond to of 1575062
 
I the paper because it gives a better explanation.

Flash, especially NAND flash is probably the easiest case for this. yield is not a problem because bad sectors have always been a problem and techniques to fuse them off are part of the package. Plus. not much in the way of heat. Dunno what the current state of DRAM structures are, so no idea if it is a candidate or not. For CPUs, the next step is to use a silicon interposer for a 2.5D stack. The interposer is just dumb silicon with wires deposited on them. AMD recently released a GPU that uses an interposer to connect to high bandwidth memory. The reason for the interposer is HBM has a 4096 bit databus.



No reason the same cannot be done for processors. Either for memory, although 4 gigabytes would be a little small, but for multiple chips. It'd be a server thing, but...