Carter,
Here is the article in EE TIMES which, in his typical overstated manner, Bruce Francis of
CNBC "reported" on. Francis's emphasis was on what the reduced line width would
mean to chip capability. He said that a chip with .05 micron lines rather than today's .25
micron, would be much faster, smaller, more powerful and "in four years could be
implemented" . Francis's interpretation of the article's meaning ignored the very real
possiblitiy that the cost per chip would also be much lower (and consequently the market
for such a chip would be much greater). Frances had no new information - simply an opinion to express. He added nothing new to the information in the article. But rather than simply report on this technological develpment, he probably managed to raise FUD to new levels by overemphasizing the possiblity that present-day processors may be made obsolete much sooner than previously forecast by the extrapolation of Moore's law by this Japanese development. He made it sound as if FUJITSU and that scary old shibboleth, the industrial behemoth Japan, Inc., was about to change the paradigm for all US semiconductor manufacturers. Frances and CNBC love FUD, it seems. I guess they think that the more of it they raise, the higher their ratings will be.
The italics are mine. This is my way of editorializing.
Paul, what do you think of the technological details and possibilities?
techweb.cmp.com
Japan sees shortcut to 0.05-micron chip
By Yoshiko Hara
TOKYO -- The Japan Science and Technology Corp. (JST), which is part of the Science
and Technology Agency, has begun a project that could enable production
of chips with 40-nanometer gate lengths within four years, lopping a decade off of the
date predicted by Moore's Law and speeding the advent of 256-Gbit DRAMs.
Based on work done at Kyoto University with the cooperation of Fujit-su Laboratories
Ltd., the program intends to develop a production tool for creating
extremely shallow ion implants--a process vital to building working transistors with very
short channels--within a few years.
In a little-noticed paper at the recent International Electron Devices Meeting in
Washington, Kyoto University and Fujitsu reported using a technique called cluster ion-
beam implantation to create a functioning p-channel MOS transistor with a 40-nm gate.
The device showed some threshold degradation - the result of the short-channel effect.
But a 50-nm transistor built with the same techniques exhibited good gain and 0.4-
mA/micron current, making for an extremely viable device.
"This result suggests that cluster ion implantation is one solution to form
the shallow implantation mandatory for ULSI," said Kyoto University professor Isao
Yamada, who heads the Ion Beam Engineering Experimental Laboratory.
A 40-nm gate length would roughly correspond to a 256-Gbit, 0.05-micron DRAM process.
Based on extrapolation of Moore's Law, such a process would be expected to appear
around 2012. But the development schedule calls for production equipment--for the ion
implant stage, at least--to be available in about four years.
"I hope cluster implantation will contribute to proving the Moore's Law
prophecy wrong, in a good direction," Yamada said.
The new technique addresses one of the most pressing problems in extreme-submicron
transistor fabrication: the short-channel effect. As the effective channel length of a
transistor shrinks below about 0.10 micron, electrical effects begin to reduce the
threshold voltage of the device, increasing leakage current and eventually making the
transistor useless.
One of the most successful approaches to moderating the short-channel effect has been
to make the channel very shallow relative to its length. That can be done by raising the
source and drain above the surface of the silicon substrate--or it can be done more
simply by creating a very shallow ion implant between the source and drain, thereby
forming a very shallow channel.
The rub is that, thus far, shallow implants have proved nearly impossible to produce.
Conventional ion-beam implanters fire a beam of individual "monomer" ions. At
conventional beam potential, those ions are driven deep into the silicon, forming a deep
channel. If the beam potential is reduced to keep the implant shallow, the individual ions'
electrical fields repel one another, scattering and diffusing the implant.
The Kyoto University approach avoids the problem by using a beam of B10H14 ions
implanted at 2 KeV with a dose of 1012 ions/cm2. Implanting clusters of 10 boron atoms
at a time reduces scatter. Yamada said that the technique permits an implant to be made
at approximately one-tenth the depth that is possible with conventional, monomer
implant tools.
Fab steps
Fabrication of the 40-nm p-channel MOSFET began with formation of a 3-micron gate-
oxide layer on an n-type silicon substrate. The researchers then built a polysilicon layer
on the oxide layer. Electron-beam lithography was used to fabricate a 0.04-micron gate,
and the ions were implanted under the gate. A separate, deeper implant was used under
the source and drain contacts.
After implant, a two-step annealing process activated the dopants and generated p+ to
form the source and drain.
Annealing at over 1,000øC is essential to prevent polysilicon gate depletion (and thus
ensure high drive current) and achieve low contact resistance. But the high temperature
causes thermal diffusion of the boron, an effect that could deepen the channel implant.
The two-step-activation annealing sequence used in the Kyoto project avoids that
problem. The gate and the deep source/drain regions were annealed at 1,000øC for 10
seconds, and the source/drain was annealed at 900øC for 10 seconds.
The procedures yielded a 7-nm ultra-shallow junction with no transient-enhanced
diffusion or thermal diffusion--the most nettlesome obstacles to successful shallow-
junction formation.
JST hopes to rush development of a production version of the experimental tool. Early
next year, a selected equipment manufacturer will start development work on a cluster
implantation system for volume production. An organization under JST will fund the
three-year project.
If the work is successful, "practical volume production using the cluster implantation will
come in about 10 years ahead of schedule," said Yamada. The extreme-submicron
project at Kyoto University grew out of a wider program of exploration. The ion-beam
laboratory has been investigating gas cluster ion-beam processing for such industrial
applications as atomic-scale surface smoothing, X-ray lithography and high-yield
sputtering. Fujitsu partnered with the university lab to explore ULSI applications.
The Ion Beam Engineering Experimental Laboratory is also collaborating with overseas
universities and research labs, including the Massachusetts Institute of Technology,
New York University, Houston University and Lawrence Livermore National Laboratory.
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Barry |
