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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: greg nus who wrote (27181)	12/26/1997 5:17:00 PM
From: Yousef	Respond to of 1573457

Greg, Re: "The doping technology they have developed is one millionth of a micron ..." You are off by a "couple orders of magnitude" ... One of the important unit processes to develop for very short gates is shallow implantation of the Source/Drain and extensions. This can also be accomplished by raising the Source/Drain with selective Si/Ge deposition. I have copied the original article on the Fujitsu process below. The Fujitsu process appears to be a "lab curiosity" at this point. Make It So, Yousef techweb.cmp.com "TOKYO -- The Japan Science and Technology Corp. (JST), which is part of the the Science and Technology Agency, has begun a project that could enable production of chips with 40-nanometer gate lengths within four years, lopping a decade off of the date predicted by Moore's Law and speeding the advent of 256-Gbit DRAMs. Based on work done at Kyoto University with the cooperation of Fujit-su Laboratories Ltd., the program intends to develop a production tool for creating extremely shallow ion implants--a process vital to building working transistors with very short channels--within a few years. In a little-noticed paper at the recent International Electron Devices Meeting in Washington, Kyoto University and Fujitsu reported using a technique called cluster ion-beam implantation to create a functioning p-channel MOS transistor with a 40-nm gate. The device showed some threshold degradation--the result of the short-channel effect. But a 50-nm transistor built with the same techniques exhibited good gain and 0.4-mA/micron current, making for an extremely viable device. "This result suggests that cluster ion implantation is one solution to form the shallow implantation mandatory for ULSI," said Kyoto University professor Isao Yamada, who heads the Ion Beam Engineering Experimental Laboratory. A 40-nm gate length would roughly correspond to a 256-Gbit, 0.05-micron DRAM process. Based on extrapolation of Moore's Law, such a process would be expected to appear around 2012. But the development schedule calls for production equipment--for the ion implant stage, at least--to be available in about four years. "I hope cluster implantation will contribute to proving the Moore's Law prophecy wrong, in a good direction," Yamada said. The new technique addresses one of the most pressing problems in extreme-submicron transistor fabrication: the short-channel effect. As the effective channel length of a transistor shrinks below about 0.10 micron, electrical effects begin to reduce the threshold voltage of the device, increasing leakage current and eventually making the transistor useless. One of the most successful approaches to moderating the short-channel effect has been to make the channel very shallow relative to its length. That can be done by raising the source and drain above the surface of the silicon substrate--or it can be done more simply by creating a very shallow ion implant between the source and drain, thereby forming a very shallow channel. The rub is that, thus far, shallow implants have proved nearly impossible to produce. Conventional ion-beam implanters fire a beam of individual "monomer" ions. At conventional beam potential, those ions are driven deep into the silicon, forming a deep channel. If the beam potential is reduced to keep the implant shallow, the individual ions' electrical fields repel one another, scattering and diffusing the implant. The Kyoto University approach avoids the problem by using a beam of B10H14 ions implanted at 2 KeV with a dose of 1012 ions/cm2. Implanting clusters of 10 boron atoms at a time reduces scatter. Yamada said that the technique permits an implant to be made at approximately one-tenth the depth that is possible with conventional, monomer implant tools. Fab steps Fabrication of the 40-nm p-channel MOSFET began with formation of a 3-micron gate-oxide layer on an n-type silicon substrate. The researchers then built a polysilicon layer on the oxide layer. Electron-beam lithography was used to fabricate a 0.04-micron gate, and the ions were implanted under the gate. A separate, deeper implant was used under the source and drain contacts. After implant, a two-step annealing process activated the dopants and generated p+ to form the source and drain. Annealing at over 1,000øC is essential to prevent polysilicon gate depletion (and thus ensure high drive current) and achieve low contact resistance. But the high temperature causes thermal diffusion of the boron, an effect that could deepen the channel implant. The two-step-activation annealing sequence used in the Kyoto project avoids that problem. The gate and the deep source/drain regions were annealed at 1,000øC for 10 seconds, and the source/drain was annealed at 900øC for 10 seconds. The procedures yielded a 7-nm ultra-shallow junction with no transient-enhanced diffusion or thermal diffusion--the most nettlesome obstacles to successful shallow-junction formation. JST hopes to rush development of a production version of the experimental tool. Early next year, a selected equipment manufacturer will start development work on a cluster implantation system for volume production. An organization under JST will fund the three-year project. If the work is successful, "practical volume production using the cluster implantation will come in about 10 years ahead of schedule," said Yamada. The extreme-submicron project at Kyoto University grew out of a wider program of exploration. The ion-beam laboratory has been investigating gas cluster ion-beam processing for such industrial applications as atomic-scale surface smoothing, X-ray lithography and high-yield sputtering. Fujitsu partnered with the university lab to explore ULSI applications. The Ion Beam Engineering Experimental Laboratory is also collaborating with overseas universities and research labs, including the Massachusetts Institute of Technology, New York University, Houston University and Lawrence Livermore National Laboratory."