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To: Elmer who wrote (43687)1/3/1998 4:27:00 AM
From: Joe NYC  Read Replies (2) | Respond to of 186894
 
Elmer,

As you probably know, socket7 locks the bus during each IO, something the P6 doesn't do. No IO cycles can be overlaped. The P6 overcomes this weakness

By the bus, do you mean memory bus? I gues we will see your thoery tested with cacheless P-II. We will see how well it perfroms with multiple of IO operations. My expectation is that the performance will drop down somewhere near MediaGX level.

Expect AGP to further complicate the issue.

I do. I think my boss was right, when he said that as you are getting closer to the right solution, things will get simpler. I wonder if the inverse is true as well, that is as you move further from the right solution, things will get more complicated.

The GTL+ buffers will scale to higher frequencies much easier regardless of the number of processors.

But with a single processor, graphics card with enough memory and no AGP, these GTL buffers are irelevant, aren't they?

Joe