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To: Aaron Cooperband who wrote (44878)1/12/1998 4:30:00 PM
From: Paul Engel  Respond to of 186894
 
Aaron - Re: " How do the additional tungsten patterns allow for this reduction? "

Let's assume that a 10% savings in area can be made per transistor.

For the onboard L1 cache on the AMD K6, there are 64 Kilobytes (2 ^16) of memory with 8 bits (or cells) per byte and 6 transistors per bit (or cell).

Thus, 3,145,578 transistirs are involved. That 10% area saved gets mutiplied by over 3 million!

Paul


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