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To: Andreas Helke who wrote (2304)	1/12/1998 8:23:00 PM
From: Norman Klein	Read Replies (1) \| Respond to of 9236

How could H&Q have the dates so screwed up?? If you read post #2290 (SteveG's H&Q report on Aware) then H&Q very clearly state that Aware will report on 1/11. Now, I believe Andreas is correct in citing "briefing.com"'s report date as the date of the release. I also don't think that H&Q made a mistake, so what are they referring to??

To: Andreas Helke who wrote (2304)	1/16/1998 1:25:00 AM
From: SteveG	Read Replies (2) \| Respond to of 9236

Yo again, Andreas- I hadn't been reading all the AWRE posts (just occasionally posting and direct responding), so I missed your previous earnings date report that I duped (although my source was different, so it may be confirmatory). Since we've had discussions about ADSL chipware before, seeing your post here I thought I'd share some recent technical stuff I've heard about Pairgain's Falcon DMT. First, did you happen to catch this report from the TXN thread?: Message 3176241 This indicates to me the likelihood of further C6X delays, which may bode well for AWRE/ADI. Then again, it could play into (as the ADCT/telecom eqps downgrades seem to) a general slowdown in deployment dollars. My guess is, until the uncertainty of the unbundle/rebundle issue is resolved (however it is), the telcos will waffle. Purportedly Pairgain's Falcon is coming along well. A custom ASIC design (generally regarded as the most efficient way to implement algorithms into silicon), the chip will be custom optimized to DMT ADSL transceiver specs such as framing, DMT modulation/demodulation, equalization, etc., and (like the new ADI mixed signal, and the planned TXN mixed DSP chip) will be a single digital functions chip. (Alcatel currently uses 3 digital function chips, and ADI currently uses 4). The Falcon is expected to offer significantly increased efficiency in power and silicon area, as well as in cost, yield, integration density, and density on system-level boards. A typical general purpose DSP takes 4-6 times the number of transistors to be equi-functional, and the DSP will still need additional ASIC blocks to perform functions such as Reed-Solomon FEC. And though I haven't heard this, I suspect that the current trend of avoiding a Y splitter at the NID, opting instead for a phone jack or modem line-filter (to prevent handset hum infiltrating into ADSL, or sub-harmonic ADSL hum infiltrating voice), may be followed by Falcon. And I haven't heard any specific Falcon release dates, only that it is coming along well. Again, the complexity of a single digital chip solution (whether ASIC or DSP) suggests the recent redirection along these lines by TXN may slow their solution to market more than originally anticipated. Steve