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To: Elmer who wrote (3898)1/16/1998 1:57:00 PM
From: Petz  Read Replies (1) | Respond to of 6843
 
Elmer, re:<The P6 generation chipsets have no concept of cache>

Then why does removing the L2 cache make the LX/BX chipsets incompatible? Please refresh me on what transactions are handled by the frontside/backside busses.

Petz