Maybe this is why ALTR trading seems suspicious:
New ASIC Architecture Offers No-NRE Conversion of Altera FPGAs
SANTA CLARA, Calif.--(BUSINESS WIRE)--JAN. 19, 1998--Santa Clara, California startup, Clear Logic, Inc. today announced a new ASIC technology that enables the conversion of Altera (NASDAQ: ALTR - news) FPGA designs to laser- configured ASICs (LASICs) directly from the customer's FPGA bitstream. The result is there is no design ''conversion'' and the ASIC is guaranteed to function identically to the ''source'' FPGA, including pin- outs and internal timing parameters.
Clear Logic's LASIC technology is based on an innovative, but simple approach to ASIC architecture and manufacturing that eliminates minimum orders, NRE charges and masks. Unlike conventional gate arrays that try to fit any and all FPGA designs into a single generic architecture, Clear Logic LASICs are designed only for Altera FPGA conversion. Each LASIC architecture is designed to accept a specific Altera FPGA family, such as the FLEX 8000. This architectural similarity enables FPGA bitstreams to be ported directly to the ASIC with absolutely no re-design, re-simulation or re-synthesis.
LASIC prototypes are available in one week and production quantities in three to four weeks. Unlike other ASICS, LASIC orders can be canceled as late as 30 days prior to delivery. Clear Logic generates all test vectors, guaranteeing 100% fault coverage, without any customer assistance or fees. All Clear Logic devices are fully tested prior to delivery to the customer. LASIC prices and power consumption are as much as 50% lower than those of their FPGA counterparts.
There are four basic elements to the Clear Logic technology: 1) a new ASIC architecture that supports specific Altera FPGA families; 2) the ClearFire laser-configuration technology that eliminates masks, results in prototypes within one week and permits each die on the wafer to be individually configured; 3) ClearShot bitstream extraction tools that can translate any Altera FPGA bitstream file into laser- configuration instructions in less than an hour; and 4) NoFault test vector generation capability that automatically generates test vectors with 100% fault coverage, based on the customer bitstream.
FPGA/Gate-array Incompatibility - According to Al Huggins, president and CEO of Clear Logic, ''The architectures of gate arrays and FPGAs are fundamentally different. Trying to ''map'' the coarse-grained implementation of an Altera FPGA design into the fine- grained architecture of a gate array is like trying to fit the proverbial square peg into a round hole. It's really hard to do and it doesn't work very well. It generally requires a complete re-mapping of the logic, with re-synthesis and re-simulation. Board re-design is also frequently necessary because the I/O characteristics of the gate array are often different from those of the FPGA. And because of the total dissimilarity of the two architectures, internal signal paths will vary dramatically between the two designs, resulting in timing problems,'' Huggins concluded.
FPGA Compatible LASIC Architectures - Clear Logic has eliminated the problem of design conversion by developing LASIC architectures that conform to those of specific, existing Altera FPGA families. LASICs are NOT general purpose gate arrays. Each LASIC family contains all of the capabilities and only the capabilities (i.e. look-up tables, registers, pin-outs, etc.) of each Altera family it is designed to support. There is, or will be, a LASIC family that supports every major Altera FPGA.
Laser Fuses Cut Die-size and Power Consumption By Up To 50% - SRAM-based FPGAs have as many as six transistors per configuration element to handle the programmable routing and switching. The large, highly capacitive routing transistors contribute to the high power consumption for which FPGAs are notorious. By comparison, just a single laser fuse performs the same function as all six of the transistors in the FPGA's programmable configuration element, but takes only 1/5 the silicon area and consumes no power. As a result, LASIC die sizes are up to 50% smaller and power consumption is up to 50% lower. LASICs also have more routing resources than the target FPGAs to ensure that FPGA functionality and timing relationships are maintained.
ClearShot EDA Tool Automates FPGA-LASIC ''Conversion'' - A key tool in the Clear Logic arsenal is the ClearShot EDA tool that automatically extracts the customer design from the bitstream file and translates it into fuse-cutting instructions for the laser. Clear Logic does not purchase customization masks. Therefore, there are no NRE charges to pass on to the customer. This process is conducted entirely by Clear Logic at the factory and takes less than one hour. No customer participation is required.
Embedded NoFault Test Capability - Clear Logic has embedded test circuitry in each LASIC device, enabling Clear Logic to ship 100% tested devices, as would any vendor of a ''standard'' product. Each logic element has three scan registers that are accessible through the I/O pins when a test mode is activated. Based on the customer bitstream, the scan registers segment the device into small blocks, called TestCells. TestCells simplify the testing of complex logic implementations, such as long chains of counters, and provide 100% fault coverage in all cases. Clear Logic's NoFault test generating capability analyses the customer bitstream and automatically generates test vectors that are customized to the customer's particular logic implementation. These test vectors are implemented using the scan registers embedded in the TestCells.
Conforms to Altera Emulation Modes Or Can Be Used to Eliminate Configuration Memory - Since Altera FPGAs are SRAM-based, they require configuration data to be loaded from non-volatile memory when they are powered-up. In order to offer plug-in compatibility, Clear Logic LASICs directly support all six Altera configuration modes. This capability enables Clear Logic LASICs to work in the same socket, in the same board that has been used for the Altera device. All the LASIC devices in the chain are guaranteed to respond in the same fashion, in the same order, as do the FPGAs of the original design.
Clear Logic LASICs can also operate without configuration memories. Since the configuration is embedded in the LASIC fuse map, ''instant-on'' operation will be identical to that of the original design, without the expense of a configuration memory, allowing designers to further reduce system costs.
Using non-volatile laser configuration instead of SRAM-based configuration bits also protects LASIC devices from power glitches.
ClearFire Laser Configuration Eliminates Minimum Orders - The masking process used to manufacture standard gate arrays requires that all the dice in a wafer lot be identical. The economic order quantity for a vendor of conventional gate arrays is wafer lots of 24 wafers. As die sizes have shrunk and wafer-sizes have grown, minimum orders have increased rapidly. It is common for a conventional ASIC vendor to require minimums of tens of thousands of units -- precluding any cost reduction path for low to medium volume applications. Clear Logic's laser-configuration process requires no masks and allows each die to be individually configured. Laser configuration eliminates both the need for minimum orders and the NRE associated with mask generation. Since several different customers' designs can be manufactured on a wafer, Clear Logic's minimum order is a single unit.
Prototypes in a Week - Unlike conventional gate arrays that must be personalized mid-way through a ten to twelve week process, ClearFire laser configuration is the last step in the manufacturing process. As a result Clear Logic prototypes can be delivered within a week of receiving the customer's bitstream file, rather than the three to six weeks required for a gate array prototype. Proprietary manufacturing enhancements that speed up the ClearFire laser configuration process enable production quantities to be delivered in three to four weeks.
30 Day Order Cancellation - Laser configuration also allows Clear Logic to offer cancellation terms comparable to those of standard products. An order for LASIC devices can be canceled as late as thirty days prior to scheduled delivery.
FLEX 8000 LASIC Support Available Now - The first LASIC family, the CL8000 series, supports designs done using Altera's FLEX 8000 family. Clear Logic has selected the FLEX 8000 family for its first LASIC conversions because of its superior architecture, strong EDA tools, and high volume.
Packaging, Pricing and Availability - The first device in the CL8000 family, the four-thousand gate CL8452A, is available now in 84-pin PLCC, 100-pin TQFP and 160-pin PQFP packages. The 160-pin PQFP CL8452AQC160-4 is priced at $14.50 for 100 units. The PLCC CL8452ALC84-4 is priced at $10.40 for 100 units. Clear Logic will add additional LASICs for the conversion of FLEX 8000 devices during 1998, as well as new architectures that support designs from other Altera device families.
Clear Logic, Inc. was founded in 1996 to offer a no-NRE, quick turn-around cost reduction path for designs that have been implemented using FPGAs. The company employs a proprietary process that converts the FPGA design to an ASIC. Clear Logic has none of the NRE charges or minimum order sizes that are typically associated with ASICs. Clear Logic devices are guaranteed to function identically to their programmable counterparts with no timing problems. Clear Logic is privately held. Integrated Device Technology, Inc. (NASDAQ: IDTI - news) is a major investor.
Note to Editors: FLEX is a registered trademark of Altera Corporation. FastTrack is a trademark of Altera Corporation. LASIC, ClearFire, ClearShot, TestCell and NoFault are trademarks of Clear Logic Inc. |
