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To: Petz who wrote (4010)	1/22/1998 4:09:00 PM
From: Doug Skrypek	Read Replies (1) \| Respond to of 6843

DLJ CONFERENCE CALL on AMD, INTC & NSM/CYRIX 1-888-209-3854

To: Petz who wrote (4010)	1/22/1998 10:35:00 PM
From: Paul Engel	Respond to of 6843

Petz - Re: " Can you give a reference that says that L2 cache will run at core speed rather than 1/2 core speed?" Here is a reference directly from Intel. Paul {========================} intel.com Pentiumr II Processor Design Enhancements Robert Colwell Microprocessor Forum October 14, 1997 "So the bottom line on Slot 1, it's P6 on a volume platform. That was our goal for it. Slot 2 stemmed from the observation that when we tuned to Slot 1 we needed another solution for Slot 2. We could have continued driving the P6 approach with two die in the package, but there is a problem when you stick an L2 inside the package: it becomes more difficult to stick multiple cache chips in there. We did -- with the P6 1Meg, we extended it one level but the ceramic package is quite full, and you couldn't stick 4 cache chips in there, and therefore the amount of cache you can stick in that product was necessarily smaller. So our solution was Slot 2, with the observation that high end market segments require the high performance, and for those segments it's okay to have higher cost to go with that. They can afford it, because of the nature of the machines. They can handle the larger cartridges because the machines are physically larger. They also want 4-way MP which requires bigger caches in order not to overload the front side bus, and it's okay to have custom SRAMS if necessary. However, these fullspeed caches require fullspeed electricals. The other piece of Slot 1, I forgot tell you it runs at half speed to the cache, and that's another reason why the cache chips don't cost as much. But for the servers you want to run them at full speed. For server workloads it makes a big difference."