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Technology Stocks : Semi Equipment Analysis -- Ignore unavailable to you. Want to Upgrade?

To: Sam who wrote (84247)	11/27/2019 1:22:59 PM
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DRAM Scaling Challenges Grow More nodes and alternative memories are in the works, but schedules remain murky. November 21st, 2019 - By: Mark LaPedus DRAM makers are pushing into the next phase of scaling, but they are facing several challenges as the memory technology approaches its physical limit. DRAM is used for main memory in systems, and today’s most advanced devices are based on roughly 18nm to 15nm processes. The physical limit for DRAM is somewhere around 10nm. There are efforts in R&D to extend the technology, and ultimately to displace it with new memory types. So far, however, there is no direct replacement. And until a new solution is in place, vendors will continue to scale the DRAM and eke out more performance, albeit in incremental steps at the current 1xnm node regime. And at future nodes, some but not all DRAM makers will make a big transition from traditional lithography to extreme ultraviolet (EUV) lithography for production in the fab. With or without EUV, DRAM vendors face higher costs and other challenges. Nevertheless, DRAM is a key part of the memory/storage hierarchy in systems. In the first tier of the hierarchy, SRAM is integrated into the processor for fast data access. DRAM, the next tier, is used for main memory. And disk drives and NAND-based solid-state storage drives (SSDs) are used for storage. The DRAM industry is a huge but tough market. DRAM vendors are in the midst of a downturn amid price pressures in the market. Yet OEMs still want faster DRAMs with more bandwidth to keep pace with the onslaught of new data-intensive applications, such as 5G and machine learning. In response, DRAM vendors are moving toward a new and faster bandwidth spec. But suppliers are no longer scaling or shrinking the DRAM at the traditional pace, which has been roughly 30% at each node. In fact, DRAM scaling is slowing, which impacts area density and cost. In DRAM, the nodes are designated by the half-pitch of the active or body of the memory cell. Today, vendors are shipping three advanced DRAM product generations at the 1xnm node regime. These three DRAM generations aren’t given a numerical node designation. The industry refers to them as simply 1xnm, 1ynm and 1znm. Then, in R&D, vendors have three more scaled generations of DRAM on the roadmap, all at the 1xnm node regime. Those are called 1anm, 1bnm and 1cnm. 1anm DRAMs are slated for 2021 or sooner. continues at semiengineering.com