January 20, 1997, Issue: 937
Section: Communications Design
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Three-chip set gets to core of ATM switch
Jeffrey C. Smith, Senior Strategic Product Architect, Integrated Device Technology Inc., Salinas, Calif.
ATM switch technology is still fairly expensive for moderately high bandwidth applications, though the cost continues to drop. A LAN switch using the latest ATM formats with the capability to transfer up to 155 Mbits/second on each of eight input and output ports, can be priced up to $15,000. A significant portion of the cost is in the physical interface, typically located in the switching-matrix memory and in the control of that switching memory.
Integrated Device Technology has been developing technology that, when coupled with innovative design techniques, will allow the core of a switch (switching-matrix memory and the control) to be available as a three-piece chip set plus some basic glue logic. The chip set will allow an eight-input by eight-output switch, with 155 Mbits/s per port, to be available to the user for about $1,000 to $2,000, including physical interfaces, manufacturing costs, and the associated glue logic. This cost estimate does represent a component savings in devices other than the switch core.
Semicustom requirement
The ATM port requirements specify anywhere from 25 Mbits/s to 2.48 Gbits/s, depending on the system positioning, with switch bandwidths being the most stringent requirement. This current semiconductor technology is available from specific custom design vendors that specialize in niche markets. The overall technology exists, but for highly integrated monolithic solutions, a semicustom memory-design house must be sought that can integrate large amounts of logic. IDT meets those design-house requirements.
ATM-cell switches typically require a minimum of eight bidirectional ports operating at 155 Mbits/s (OC-3), or 1.24 Gbits/s (OC-24), both in and out (2.48 Gbits/s total). Equally important, ATM data is generally transmitted serially. Within the switch system, the data is converted from serial to parallel and then manipulated, rerouted, and converted back to serial for output transmission. Though data conversion may seem insignificant in the context of switch-design specifications, reducing the conversion factors directly decrease the overall switch delay, which is important for reducing the transmission delay from endpoint to endpoint. More importantly, the reduction of parallel bits per port does reduce the number of pins required for a monolithic solution, directly reducing the cost of each switch device.
IDT has developed technology, and is now developing components, that meet both bandwidth and cost requirements for ATM switch technology to become widely accepted. A typical application of eight ATM ports at 155 Mbits/s would require one central switch memory, one switch controller, and one generic call-setup manager (the central processing unit)
The central switch memory will be available in a 208-pin plastic quad flat pack, the switch controller is to be available in a 100-pin thin quad flat pack, and the call-setup CPU as any general-application RISC processor of R3041-derivative generation or above.
Other components required depend on the individual design of the user. Specific differences would be interface methods such as segmentation-and-reassembly (SAR) devices, and any other interface conversion chips.
IDT's recent entry into the ATM market has now evolved to development of the central-switch-memory chip. Its basic concept is eight input ports and eight output ports, with a total cell storage capacity of 8k cells within the memory core. The ports can each handle between 52 and 56 bytes of information, as programmed at the switch system power-up initialization, with 53 bytes comprising a typical ATM cell. The typical ATM cell of 53 bytes includes 48 bytes of payload and 5 bytes of header information, where one of the header bytes is the CRC information, and therefore may be deleted from the switch path as long as it is added at the exit of the switch path. Any other information required by an individual user's switch architecture may be transmitted in the other three bytes available (56 bytes total)
Each port in the memory is designated as a DPI-bus port's interface. A data-port-interface basic bus is specified as four bits of data, a control clock, and a frame indicator. Each DPI bus is designated for use as a 155-Mbit/s ATM port, which may be combined in four-bit increments of 155 Mbits/s up to a single bus of 32-bit 1.24-Gbits/s for all eight ports combined. The ports allow for the 155-Mbits/s to 1.24 Gbits/s input to (or output from) the central switch memory. The memory is organized essentially as an 8k-cell array (4 Mbits total memory size), where the cell of an individual port enters through an individual port. After the individual cell enters the port, the frame marker indicates the access to the central-memory array to begin.
Header modification
After a cell-frame indication, there is another port, connected to the central-memory controller, that modifies the ATM header, and then directs the cell as to where it is to be stored. At this time the cell is stored in a single parallel operation and left to be retrieved in a similar manner. This is the basic operation of the central memory.
Packetizing of the ATM cells has also been included, to allow Ethernet or any other packet-switching technologies to be transmitted through the central-memory chip without any interruption. The capability exists to tag a packet and transfer it as a whole, once the full packet has been received. This basic Ethernet requirement has been incorporated to allow the easiest possible format conversion within a single chip. The controller keeps track of the packetized cells via the call setup, and therefore allows the whole packet transfer to be done upon receipt. The controller interface is a 32-bit I/O port, plus additional control bits.
The basic architecture of the central switch memory allows for various switching configurations. These include the basic eight-ports-in-by-eight-ports-out at 155 Mbits/s each; an 8:1 concentrator for eight ports in at 155 Mbits/s each by one output port at 1.24 Gbits/s; a 1:8 expander for one input port at 1.24 Gbits/s by eight ports out at 155 Mbits/s each; and a mixture of these options.
The central-memory controller is the brains of the switch chip set, and is the central-memory data-path manager. The controller handles from one to four data-path chips of 1.24-Gbit/s I/O bandwidth each, where the limitation is the header manipulation and the central-memory storage capability. There is a total of 8,000 virtual connections available (8 x 1,024 call setups possible) per controller. The central-memory storage mapping from the controller allows for up to 8k cells x four central-memory buffers (32k cells total), where there is a queue-length limit that can be set per connection.
Output multicasting is also available, set by the internal-output-bus queuing and the output-cell-header manipulation. Internally, there is variable bit rate (VBR) and constant bit rate (CBR) control available, as well as internal explicit forward congestion indication (EFCI), available bit rate (ABR), and full external ABR capability.
Basically, the controller meets the current ATM UNI 4.0 specs.
Commands keep comin'
The controller constantly sends commands to the data-path chip (the central memory). These commands poll the status indication for the received cells and the emptied buffers of the output ports. This information is used to initiate the cell transfers between the ports, and the DRAM memory core of the data-path chip. The memory controller has time to refresh the central memory, at intervals between the cells to be transferred and also when there are not any cells to be transferred.
The data-path chip is a 4-Mbit memory that stores 8k cells (8k x 52 bytes up to 56 bytes), so 8,000 locations must be refreshed periodically. The refresh of any individual location must be done every 8 milliseconds at a minimum. The controller does not discriminate on stored data vs. unused locations, i.e., queued data is refreshed as well as free locations.
Refreshing is done over the controller to the data-path chip bus and the respective control bits, where the command for a refresh is delivered but not the address to be refreshed. The refresh address is kept track of and supplied internally by the data-path chip. The refresh rate itself is programmed into a counter register available to the controller's state machine to allow a variable rate of time, as determined by the user, for each individual system.
The data-path chip architecture handles multicast and broadcast traffic.
The two-part call-setup manager interaction with the switch controller is very simple. One part is the memory-controller initialization at system power-up, and then each virtual-connection (VC) call setup; the second is the main system interaction performed at power-up. This also includes downstream system VC bandwidth adjustments. For a general multimedia application, one central-memory chip and one controller is utilized along with external logic, as required. This provides a price-competitive solution with the benefit of simplicity and compactness, ideal for a set-top box.
Copyright r 1997 CMP Media Inc.
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