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To: billwot who wrote (46608)1/28/1998 12:21:00 PM
From: Paul Engel  Read Replies (2) | Respond to of 186894
 
Bill - Re: "...the performance differences will be between the "cacheless" chip and its full-featured counterpart?"

The Cacheless chip will be slower - memory accesses will have to occur from main memory - which will run at 66 or 100 MHz instead of the 133 MHz (assuming a 266 MHz CPU speed).

This all presupposes that Intel uses the same Slot 1 interface for the Covington - in which the L2 data bus cannot be brought out to the motherboard.

On the other hand, if Intel changes the packaging, the L2 cache bus could be brought out to the motherboard where an external L2 cache can be provided by the MB manufacturer.

Bear in mind, Intel's motives seem to be cost reduction - not system performance.

Paul